[PATCH] D145085: [RISCV] Lower fixed length interleaved accesses via vssegN/vlsegN

[Luke Lau via Phabricator via llvm-commits]

luke updated this revision to Diff 508551.
luke added a comment.

Address review comments


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D145085/new/

https://reviews.llvm.org/D145085

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
  llvm/test/CodeGen/RISCV/O3-pipeline.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access-zve32x.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shufflevector-vnsrl.ll
  llvm/test/Transforms/InterleavedAccess/RISCV/interleaved-accesses.ll
  llvm/test/Transforms/InterleavedAccess/RISCV/zve32x.ll
  llvm/test/Transforms/InterleavedAccess/RISCV/zvl32b.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D145085.508551.patch
Type: text/x-patch
Size: 105218 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20230327/9f534f4e/attachment.bin>