[PATCH] D145301: Add more efficient vector bitcast for AArch64

[Lawrence Benson via Phabricator via llvm-commits]

lawben added a comment.

@Sp00ph  Your example would not be optimized. The issue with that example is: how is a `bitcast` to `i1` defined? The current logic in LLVM uses the least significant bit. But this trick does not work in that case, as we use bits 0 to n for lanes 0 to n, so we only use the least significant one for lane 0. If we have a comparison, we know that all bits are 1 or all bits a 0, so if the least significant one is equal to all others. Without a comparison, we could shift the least significant bit and then doe the rest, but that would need an extra instruction. Maybe this could be added in a follow-up? I'm happy to discuss options here. The current approach is a bit more conservative.


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https://reviews.llvm.org/D145301