[PATCH] D146245: [RISCV] Lower inline asm m with offset to register+imm.

[Craig Topper via Phabricator via llvm-commits]

craig.topper requested changes to this revision.
craig.topper added a comment.
This revision now requires changes to proceed.

LGTM



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Comment at: llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp:185
+  const MachineOperand &AddrReg = MI->getOperand(OpNo);
+  assert(MI->getNumOperands() > OpNo + 1 && "Expanded additional operand");
+  const MachineOperand &DispImm = MI->getOperand(OpNo + 1);
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Is "Expanded" here supposed to be "Expected"?


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Comment at: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp:2102
+    SDValue Op0, Op1;
+    assert(SelectAddrRegImm(Op, Op0, Op1) &&
+           "SelectAddrRegImm should always succeed");
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The body of an `assert` is not executed in release builds. SelectAddRegImm will not be called.


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  https://reviews.llvm.org/D146245/new/

https://reviews.llvm.org/D146245