[llvm] 3cf7e35 - [RISCV] Made division pseudoinstructions SEW-aware
Nitin John Raj via llvm-commits
llvm-commits at lists.llvm.org
Fri Mar 24 16:41:07 PDT 2023
Author: Nitin John Raj
Date: 2023-03-24T16:33:24-07:00
New Revision: 3cf7e3518072c41757381b1490172c17e57defe4
URL: https://github.com/llvm/llvm-project/commit/3cf7e3518072c41757381b1490172c17e57defe4
DIFF: https://github.com/llvm/llvm-project/commit/3cf7e3518072c41757381b1490172c17e57defe4.diff
LOG: [RISCV] Made division pseudoinstructions SEW-aware
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
llvm/lib/Target/RISCV/RISCVScheduleV.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index c385224a86c9..327b3c544c97 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -2033,6 +2033,10 @@ multiclass VPseudoBinaryFV_VV<LMULInfo m, string Constraint = ""> {
defm _VV : VPseudoBinary<m.vrclass, m.vrclass, m.vrclass, m, Constraint>;
}
+multiclass VPseudoBinaryFV_VV_E<LMULInfo m, int sew, string Constraint = ""> {
+ defm _VV : VPseudoBinary_E<m.vrclass, m.vrclass, m.vrclass, m, sew, Constraint>;
+}
+
multiclass VPseudoVGTR_VV_EEW<int eew, string Constraint = ""> {
foreach m = MxList in {
defvar mx = m.MX;
@@ -2060,6 +2064,10 @@ multiclass VPseudoBinaryV_VX<LMULInfo m, string Constraint = ""> {
defm "_VX" : VPseudoBinary<m.vrclass, m.vrclass, GPR, m, Constraint>;
}
+multiclass VPseudoBinaryV_VX_E<LMULInfo m, int sew, string Constraint = ""> {
+ defm "_VX" : VPseudoBinary_E<m.vrclass, m.vrclass, GPR, m, sew, Constraint>;
+}
+
multiclass VPseudoVSLD1_VX<string Constraint = ""> {
foreach m = MxList in {
defvar mx = m.MX;
@@ -2077,6 +2085,12 @@ multiclass VPseudoBinaryV_VF<LMULInfo m, FPR_Info f, string Constraint = ""> {
f.fprclass, m, Constraint>;
}
+multiclass VPseudoBinaryV_VF_E<LMULInfo m, int sew, FPR_Info f,
+ string Constraint = ""> {
+ defm "_V" # f.FX : VPseudoBinary_E<m.vrclass, m.vrclass,
+ f.fprclass, m, sew, Constraint>;
+}
+
multiclass VPseudoVSLD1_VF<string Constraint = ""> {
foreach f = FPList in {
foreach m = f.MxList in {
@@ -2621,15 +2635,18 @@ multiclass VPseudoVMUL_VV_VX {
multiclass VPseudoVDIV_VV_VX {
foreach m = MxList in {
defvar mx = m.MX;
- defvar WriteVIDivV_MX = !cast<SchedWrite>("WriteVIDivV_" # mx);
- defvar WriteVIDivX_MX = !cast<SchedWrite>("WriteVIDivX_" # mx);
- defvar ReadVIDivV_MX = !cast<SchedRead>("ReadVIDivV_" # mx);
- defvar ReadVIDivX_MX = !cast<SchedRead>("ReadVIDivX_" # mx);
-
- defm "" : VPseudoBinaryV_VV<m>,
- Sched<[WriteVIDivV_MX, ReadVIDivV_MX, ReadVIDivV_MX, ReadVMask]>;
- defm "" : VPseudoBinaryV_VX<m>,
- Sched<[WriteVIDivX_MX, ReadVIDivV_MX, ReadVIDivX_MX, ReadVMask]>;
+ defvar sews = SchedSEWSet<mx>.val;
+ foreach e = sews in {
+ defvar WriteVIDivV_MX_E = !cast<SchedWrite>("WriteVIDivV_" # mx # "_E" # e);
+ defvar WriteVIDivX_MX_E = !cast<SchedWrite>("WriteVIDivX_" # mx # "_E" # e);
+ defvar ReadVIDivV_MX_E = !cast<SchedRead>("ReadVIDivV_" # mx # "_E" # e);
+ defvar ReadVIDivX_MX_E = !cast<SchedRead>("ReadVIDivX_" # mx # "_E" # e);
+
+ defm "" : VPseudoBinaryV_VV_E<m, e>,
+ Sched<[WriteVIDivV_MX_E, ReadVIDivV_MX_E, ReadVIDivV_MX_E, ReadVMask]>;
+ defm "" : VPseudoBinaryV_VX_E<m, e>,
+ Sched<[WriteVIDivX_MX_E, ReadVIDivV_MX_E, ReadVIDivX_MX_E, ReadVMask]>;
+ }
}
}
@@ -2659,22 +2676,28 @@ multiclass VPseudoVFMUL_VV_VF {
multiclass VPseudoVFDIV_VV_VF {
foreach m = MxListF in {
defvar mx = m.MX;
- defvar WriteVFDivV_MX = !cast<SchedWrite>("WriteVFDivV_" # mx);
- defvar ReadVFDivV_MX = !cast<SchedRead>("ReadVFDivV_" # mx);
+ defvar sews = SchedSEWSet<mx>.val;
+ foreach e = sews in {
+ defvar WriteVFDivV_MX_E = !cast<SchedWrite>("WriteVFDivV_" # mx # "_E" # e);
+ defvar ReadVFDivV_MX_E = !cast<SchedRead>("ReadVFDivV_" # mx # "_E" # e);
- defm "" : VPseudoBinaryFV_VV<m>,
- Sched<[WriteVFDivV_MX, ReadVFDivV_MX, ReadVFDivV_MX, ReadVMask]>;
+ defm "" : VPseudoBinaryFV_VV_E<m, e>,
+ Sched<[WriteVFDivV_MX_E, ReadVFDivV_MX_E, ReadVFDivV_MX_E, ReadVMask]>;
+ }
}
foreach f = FPList in {
foreach m = f.MxList in {
defvar mx = m.MX;
- defvar WriteVFDivF_MX = !cast<SchedWrite>("WriteVFDivF_" # mx);
- defvar ReadVFDivV_MX = !cast<SchedRead>("ReadVFDivV_" # mx);
- defvar ReadVFDivF_MX = !cast<SchedRead>("ReadVFDivF_" # mx);
+ defvar sews = SchedSEWSet<mx>.val;
+ foreach e = sews in {
+ defvar WriteVFDivF_MX_E = !cast<SchedWrite>("WriteVFDivF_" # mx # "_E" # e);
+ defvar ReadVFDivV_MX_E = !cast<SchedRead>("ReadVFDivV_" # mx # "_E" # e);
+ defvar ReadVFDivF_MX_E = !cast<SchedRead>("ReadVFDivF_" # mx # "_E" # e);
- defm "" : VPseudoBinaryV_VF<m, f>,
- Sched<[WriteVFDivF_MX, ReadVFDivV_MX, ReadVFDivF_MX, ReadVMask]>;
+ defm "" : VPseudoBinaryV_VF_E<m, e, f>,
+ Sched<[WriteVFDivF_MX_E, ReadVFDivV_MX_E, ReadVFDivF_MX_E, ReadVMask]>;
+ }
}
}
}
@@ -2683,11 +2706,15 @@ multiclass VPseudoVFRDIV_VF {
foreach f = FPList in {
foreach m = f.MxList in {
defvar mx = m.MX;
- defvar WriteVFDivF_MX = !cast<SchedWrite>("WriteVFDivF_" # mx);
- defvar ReadVFDivV_MX = !cast<SchedRead>("ReadVFDivV_" # mx);
- defvar ReadVFDivF_MX = !cast<SchedRead>("ReadVFDivF_" # mx);
- defm "" : VPseudoBinaryV_VF<m, f>,
- Sched<[WriteVFDivF_MX, ReadVFDivV_MX, ReadVFDivF_MX, ReadVMask]>;
+ defvar sews = SchedSEWSet<mx>.val;
+ foreach e = sews in {
+ defvar WriteVFDivF_MX_E = !cast<SchedWrite>("WriteVFDivF_" # mx # "_E" # e);
+ defvar ReadVFDivV_MX_E = !cast<SchedRead>("ReadVFDivV_" # mx # "_E" # e);
+ defvar ReadVFDivF_MX_E = !cast<SchedRead>("ReadVFDivF_" # mx # "_E" # e);
+
+ defm "" : VPseudoBinaryV_VF_E<m, e, f>,
+ Sched<[WriteVFDivF_MX_E, ReadVFDivV_MX_E, ReadVFDivF_MX_E, ReadVMask]>;
+ }
}
}
}
@@ -4503,6 +4530,16 @@ multiclass VPatBinaryV_VV<string intrinsic, string instruction,
vti.RegClass, vti.RegClass>;
}
+multiclass VPatBinaryV_VV_E<string intrinsic, string instruction,
+ list<VTypeInfo> vtilist> {
+ foreach vti = vtilist in
+ defm : VPatBinaryTA<intrinsic,
+ instruction # "_VV_" # vti.LMul.MX # "_E" # vti.SEW,
+ vti.Vector, vti.Vector, vti.Vector,vti.Mask,
+ vti.Log2SEW, vti.RegClass,
+ vti.RegClass, vti.RegClass>;
+}
+
multiclass VPatBinaryV_VV_INT_E<string intrinsic, string instruction,
list<VTypeInfo> vtilist> {
foreach vti = vtilist in {
@@ -4545,6 +4582,18 @@ multiclass VPatBinaryV_VX<string intrinsic, string instruction,
}
}
+multiclass VPatBinaryV_VX_E<string intrinsic, string instruction,
+ list<VTypeInfo> vtilist> {
+ foreach vti = vtilist in {
+ defvar kind = "V"#vti.ScalarSuffix;
+ defm : VPatBinaryTA<intrinsic,
+ instruction#"_"#kind#"_"#vti.LMul.MX#"_E"#vti.SEW,
+ vti.Vector, vti.Vector, vti.Scalar, vti.Mask,
+ vti.Log2SEW, vti.RegClass,
+ vti.RegClass, vti.ScalarRegClass>;
+ }
+}
+
multiclass VPatBinaryV_VX_INT<string intrinsic, string instruction,
list<VTypeInfo> vtilist> {
foreach vti = vtilist in
@@ -4810,6 +4859,11 @@ multiclass VPatBinaryV_VV_VX<string intrinsic, string instruction,
: VPatBinaryV_VV<intrinsic, instruction, vtilist>,
VPatBinaryV_VX<intrinsic, instruction, vtilist>;
+multiclass VPatBinaryV_VV_VX_E<string intrinsic, string instruction,
+ list<VTypeInfo> vtilist>
+ : VPatBinaryV_VV_E<intrinsic, instruction, vtilist>,
+ VPatBinaryV_VX_E<intrinsic, instruction, vtilist>;
+
multiclass VPatBinaryV_VX_VI<string intrinsic, string instruction,
list<VTypeInfo> vtilist>
: VPatBinaryV_VX<intrinsic, instruction, vtilist>,
@@ -6091,10 +6145,10 @@ defm : VPatBinaryV_VV_VX<"int_riscv_vmulhsu", "PseudoVMULHSU", AllIntegerVectors
//===----------------------------------------------------------------------===//
// 11.11. Vector Integer Divide Instructions
//===----------------------------------------------------------------------===//
-defm : VPatBinaryV_VV_VX<"int_riscv_vdivu", "PseudoVDIVU", AllIntegerVectors>;
-defm : VPatBinaryV_VV_VX<"int_riscv_vdiv", "PseudoVDIV", AllIntegerVectors>;
-defm : VPatBinaryV_VV_VX<"int_riscv_vremu", "PseudoVREMU", AllIntegerVectors>;
-defm : VPatBinaryV_VV_VX<"int_riscv_vrem", "PseudoVREM", AllIntegerVectors>;
+defm : VPatBinaryV_VV_VX_E<"int_riscv_vdivu", "PseudoVDIVU", AllIntegerVectors>;
+defm : VPatBinaryV_VV_VX_E<"int_riscv_vdiv", "PseudoVDIV", AllIntegerVectors>;
+defm : VPatBinaryV_VV_VX_E<"int_riscv_vremu", "PseudoVREMU", AllIntegerVectors>;
+defm : VPatBinaryV_VV_VX_E<"int_riscv_vrem", "PseudoVREM", AllIntegerVectors>;
//===----------------------------------------------------------------------===//
// 11.12. Vector Widening Integer Multiply Instructions
@@ -6207,8 +6261,8 @@ defm : VPatBinaryW_WV_WX<"int_riscv_vfwsub_w", "PseudoVFWSUB", AllWidenableFloat
// 13.4. Vector Single-Width Floating-Point Multiply/Divide Instructions
//===----------------------------------------------------------------------===//
defm : VPatBinaryV_VV_VX<"int_riscv_vfmul", "PseudoVFMUL", AllFloatVectors>;
-defm : VPatBinaryV_VV_VX<"int_riscv_vfdiv", "PseudoVFDIV", AllFloatVectors>;
-defm : VPatBinaryV_VX<"int_riscv_vfrdiv", "PseudoVFRDIV", AllFloatVectors>;
+defm : VPatBinaryV_VV_VX_E<"int_riscv_vfdiv", "PseudoVFDIV", AllFloatVectors>;
+defm : VPatBinaryV_VX_E<"int_riscv_vfrdiv", "PseudoVFRDIV", AllFloatVectors>;
//===----------------------------------------------------------------------===//
// 13.5. Vector Widening Floating-Point Multiply
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
index 23fb5364ab16..ee75392ef170 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
@@ -88,6 +88,23 @@ class VPatBinarySDNode_VV<SDPatternOperator vop,
op_reg_class:$rs2,
avl, sew)>;
+class VPatBinarySDNode_VV_E<SDPatternOperator vop,
+ string instruction_name,
+ ValueType result_type,
+ ValueType op_type,
+ int log2sew,
+ LMULInfo vlmul,
+ int sew,
+ OutPatFrag avl,
+ VReg op_reg_class> :
+ Pat<(result_type (vop
+ (op_type op_reg_class:$rs1),
+ (op_type op_reg_class:$rs2))),
+ (!cast<Instruction>(instruction_name#"_VV_"# vlmul.MX#"_E"#sew)
+ op_reg_class:$rs1,
+ op_reg_class:$rs2,
+ avl, log2sew)>;
+
class VPatBinarySDNode_XI<SDPatternOperator vop,
string instruction_name,
string suffix,
@@ -107,6 +124,26 @@ class VPatBinarySDNode_XI<SDPatternOperator vop,
xop_kind:$rs2,
avl, sew)>;
+class VPatBinarySDNode_XI_E<SDPatternOperator vop,
+ string instruction_name,
+ string suffix,
+ ValueType result_type,
+ ValueType vop_type,
+ int log2sew,
+ LMULInfo vlmul,
+ int sew,
+ OutPatFrag avl,
+ VReg vop_reg_class,
+ ComplexPattern SplatPatKind,
+ DAGOperand xop_kind> :
+ Pat<(result_type (vop
+ (vop_type vop_reg_class:$rs1),
+ (vop_type (SplatPatKind xop_kind:$rs2)))),
+ (!cast<Instruction>(instruction_name#_#suffix#_# vlmul.MX#"_E"#sew)
+ vop_reg_class:$rs1,
+ xop_kind:$rs2,
+ avl, log2sew)>;
+
multiclass VPatBinarySDNode_VV_VX<SDPatternOperator vop, string instruction_name> {
foreach vti = AllIntegerVectors in {
def : VPatBinarySDNode_VV<vop, instruction_name,
@@ -119,6 +156,19 @@ multiclass VPatBinarySDNode_VV_VX<SDPatternOperator vop, string instruction_name
}
}
+multiclass VPatBinarySDNode_VV_VX_E<SDPatternOperator vop,
+ string instruction_name> {
+ foreach vti = AllIntegerVectors in {
+ def : VPatBinarySDNode_VV_E<vop, instruction_name,
+ vti.Vector, vti.Vector, vti.Log2SEW,
+ vti.LMul, vti.SEW, vti.AVL, vti.RegClass>;
+ def : VPatBinarySDNode_XI_E<vop, instruction_name, "VX",
+ vti.Vector, vti.Vector, vti.Log2SEW,
+ vti.LMul, vti.SEW, vti.AVL, vti.RegClass,
+ SplatPat, GPR>;
+ }
+}
+
multiclass VPatBinarySDNode_VV_VX_VI<SDPatternOperator vop, string instruction_name,
Operand ImmType = simm5>
: VPatBinarySDNode_VV_VX<vop, instruction_name> {
@@ -148,6 +198,24 @@ class VPatBinarySDNode_VF<SDPatternOperator vop,
(xop_type xop_kind:$rs2),
avl, sew)>;
+class VPatBinarySDNode_VF_E<SDPatternOperator vop,
+ string instruction_name,
+ ValueType result_type,
+ ValueType vop_type,
+ ValueType xop_type,
+ int log2sew,
+ LMULInfo vlmul,
+ int sew,
+ OutPatFrag avl,
+ VReg vop_reg_class,
+ DAGOperand xop_kind> :
+ Pat<(result_type (vop (vop_type vop_reg_class:$rs1),
+ (vop_type (SplatFPOp xop_kind:$rs2)))),
+ (!cast<Instruction>(instruction_name#"_"#vlmul.MX#"_E"#sew)
+ vop_reg_class:$rs1,
+ (xop_type xop_kind:$rs2),
+ avl, log2sew)>;
+
multiclass VPatBinaryFPSDNode_VV_VF<SDPatternOperator vop, string instruction_name> {
foreach vti = AllFloatVectors in {
def : VPatBinarySDNode_VV<vop, instruction_name,
@@ -160,6 +228,19 @@ multiclass VPatBinaryFPSDNode_VV_VF<SDPatternOperator vop, string instruction_na
}
}
+multiclass VPatBinaryFPSDNode_VV_VF_E<SDPatternOperator vop,
+ string instruction_name> {
+ foreach vti = AllFloatVectors in {
+ def : VPatBinarySDNode_VV_E<vop, instruction_name,
+ vti.Vector, vti.Vector, vti.Log2SEW,
+ vti.LMul, vti.SEW, vti.AVL, vti.RegClass>;
+ def : VPatBinarySDNode_VF_E<vop, instruction_name#"_V"#vti.ScalarSuffix,
+ vti.Vector, vti.Vector, vti.Scalar,
+ vti.Log2SEW, vti.LMul, vti.SEW, vti.AVL,
+ vti.RegClass, vti.ScalarRegClass>;
+ }
+}
+
multiclass VPatBinaryFPSDNode_R_VF<SDPatternOperator vop, string instruction_name> {
foreach fvti = AllFloatVectors in
def : Pat<(fvti.Vector (vop (fvti.Vector (SplatFPOp fvti.Scalar:$rs2)),
@@ -170,6 +251,17 @@ multiclass VPatBinaryFPSDNode_R_VF<SDPatternOperator vop, string instruction_nam
fvti.AVL, fvti.Log2SEW)>;
}
+multiclass VPatBinaryFPSDNode_R_VF_E<SDPatternOperator vop,
+ string instruction_name> {
+ foreach fvti = AllFloatVectors in
+ def : Pat<(fvti.Vector (vop (fvti.Vector (SplatFPOp fvti.Scalar:$rs2)),
+ (fvti.Vector fvti.RegClass:$rs1))),
+ (!cast<Instruction>(instruction_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX#"_E"#fvti.SEW)
+ fvti.RegClass:$rs1,
+ (fvti.Scalar fvti.ScalarRegClass:$rs2),
+ fvti.AVL, fvti.Log2SEW)>;
+}
+
multiclass VPatIntegerSetCCSDNode_VV<string instruction_name,
CondCode cc> {
foreach vti = AllIntegerVectors in {
@@ -723,10 +815,10 @@ defm : VPatBinarySDNode_VV_VX<mulhs, "PseudoVMULH">;
defm : VPatBinarySDNode_VV_VX<mulhu, "PseudoVMULHU">;
// 11.11. Vector Integer Divide Instructions
-defm : VPatBinarySDNode_VV_VX<udiv, "PseudoVDIVU">;
-defm : VPatBinarySDNode_VV_VX<sdiv, "PseudoVDIV">;
-defm : VPatBinarySDNode_VV_VX<urem, "PseudoVREMU">;
-defm : VPatBinarySDNode_VV_VX<srem, "PseudoVREM">;
+defm : VPatBinarySDNode_VV_VX_E<udiv, "PseudoVDIVU">;
+defm : VPatBinarySDNode_VV_VX_E<sdiv, "PseudoVDIV">;
+defm : VPatBinarySDNode_VV_VX_E<urem, "PseudoVREMU">;
+defm : VPatBinarySDNode_VV_VX_E<srem, "PseudoVREM">;
// 11.12. Vector Widening Integer Multiply Instructions
defm : VPatWidenBinarySDNode_VV_VX<mul, sext_oneuse, sext_oneuse,
@@ -836,8 +928,8 @@ defm : VPatWidenBinaryFPSDNode_VV_VF_WV_WF<fsub, "PseudoVFWSUB">;
// 13.4. Vector Single-Width Floating-Point Multiply/Divide Instructions
defm : VPatBinaryFPSDNode_VV_VF<any_fmul, "PseudoVFMUL">;
-defm : VPatBinaryFPSDNode_VV_VF<any_fdiv, "PseudoVFDIV">;
-defm : VPatBinaryFPSDNode_R_VF<any_fdiv, "PseudoVFRDIV">;
+defm : VPatBinaryFPSDNode_VV_VF_E<any_fdiv, "PseudoVFDIV">;
+defm : VPatBinaryFPSDNode_R_VF_E<any_fdiv, "PseudoVFRDIV">;
// 13.5. Vector Widening Floating-Point Multiply Instructions
defm : VPatWidenBinaryFPSDNode_VV_VF<fmul, "PseudoVFWMUL">;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
index bca0511c98a3..218610b74208 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
@@ -464,6 +464,32 @@ multiclass VPatBinaryVL_V<SDPatternOperator vop,
(mask_type V0), GPR:$vl, sew, TAIL_AGNOSTIC)>;
}
+multiclass VPatBinaryVL_V_E<SDPatternOperator vop,
+ string instruction_name,
+ string suffix,
+ ValueType result_type,
+ ValueType op1_type,
+ ValueType op2_type,
+ ValueType mask_type,
+ int log2sew,
+ LMULInfo vlmul,
+ int sew,
+ VReg result_reg_class,
+ VReg op1_reg_class,
+ VReg op2_reg_class> {
+ def : Pat<(result_type (vop
+ (op1_type op1_reg_class:$rs1),
+ (op2_type op2_reg_class:$rs2),
+ (result_type result_reg_class:$merge),
+ (mask_type V0),
+ VLOpFrag)),
+ (!cast<Instruction>(instruction_name#"_"#suffix#"_"# vlmul.MX#"_E"# sew#"_MASK")
+ result_reg_class:$merge,
+ op1_reg_class:$rs1,
+ op2_reg_class:$rs2,
+ (mask_type V0), GPR:$vl, log2sew, TAIL_AGNOSTIC)>;
+}
+
multiclass VPatTiedBinaryNoMaskVL_V<SDNode vop,
string instruction_name,
string suffix,
@@ -524,6 +550,33 @@ multiclass VPatBinaryVL_XI<SDPatternOperator vop,
(mask_type V0), GPR:$vl, sew, TAIL_AGNOSTIC)>;
}
+multiclass VPatBinaryVL_XI_E<SDPatternOperator vop,
+ string instruction_name,
+ string suffix,
+ ValueType result_type,
+ ValueType vop1_type,
+ ValueType vop2_type,
+ ValueType mask_type,
+ int log2sew,
+ LMULInfo vlmul,
+ int sew,
+ VReg result_reg_class,
+ VReg vop_reg_class,
+ ComplexPattern SplatPatKind,
+ DAGOperand xop_kind> {
+ def : Pat<(result_type (vop
+ (vop1_type vop_reg_class:$rs1),
+ (vop2_type (SplatPatKind (XLenVT xop_kind:$rs2))),
+ (result_type result_reg_class:$merge),
+ (mask_type V0),
+ VLOpFrag)),
+ (!cast<Instruction>(instruction_name#_#suffix#_# vlmul.MX#"_E"# sew#"_MASK")
+ result_reg_class:$merge,
+ vop_reg_class:$rs1,
+ xop_kind:$rs2,
+ (mask_type V0), GPR:$vl, log2sew, TAIL_AGNOSTIC)>;
+}
+
multiclass VPatBinaryVL_VV_VX<SDPatternOperator vop, string instruction_name> {
foreach vti = AllIntegerVectors in {
defm : VPatBinaryVL_V<vop, instruction_name, "VV",
@@ -537,6 +590,20 @@ multiclass VPatBinaryVL_VV_VX<SDPatternOperator vop, string instruction_name> {
}
}
+multiclass VPatBinaryVL_VV_VX_E<SDPatternOperator vop,
+ string instruction_name> {
+ foreach vti = AllIntegerVectors in {
+ defm : VPatBinaryVL_V_E<vop, instruction_name, "VV",
+ vti.Vector, vti.Vector, vti.Vector, vti.Mask,
+ vti.Log2SEW, vti.LMul, vti.SEW,
+ vti.RegClass, vti.RegClass, vti.RegClass>;
+ defm : VPatBinaryVL_XI_E<vop, instruction_name, "VX",
+ vti.Vector, vti.Vector, vti.Vector, vti.Mask,
+ vti.Log2SEW, vti.LMul, vti.SEW,
+ vti.RegClass, vti.RegClass, SplatPat, GPR>;
+ }
+}
+
multiclass VPatBinaryVL_VV_VX_VI<SDPatternOperator vop, string instruction_name,
Operand ImmType = simm5>
: VPatBinaryVL_VV_VX<vop, instruction_name> {
@@ -625,6 +692,29 @@ multiclass VPatBinaryVL_VF<SDPatternOperator vop,
(mask_type V0), GPR:$vl, sew, TAIL_AGNOSTIC)>;
}
+multiclass VPatBinaryVL_VF_E<SDPatternOperator vop,
+ string instruction_name,
+ ValueType result_type,
+ ValueType vop_type,
+ ValueType mask_type,
+ int log2sew,
+ LMULInfo vlmul,
+ int sew,
+ VReg result_reg_class,
+ VReg vop_reg_class,
+ RegisterClass scalar_reg_class> {
+ def : Pat<(result_type (vop (vop_type vop_reg_class:$rs1),
+ (vop_type (SplatFPOp scalar_reg_class:$rs2)),
+ (result_type result_reg_class:$merge),
+ (mask_type V0),
+ VLOpFrag)),
+ (!cast<Instruction>(instruction_name#"_"#vlmul.MX#"_E"#sew#"_MASK")
+ result_reg_class:$merge,
+ vop_reg_class:$rs1,
+ scalar_reg_class:$rs2,
+ (mask_type V0), GPR:$vl, log2sew, TAIL_AGNOSTIC)>;
+}
+
multiclass VPatBinaryFPVL_VV_VF<SDPatternOperator vop, string instruction_name> {
foreach vti = AllFloatVectors in {
defm : VPatBinaryVL_V<vop, instruction_name, "VV",
@@ -638,6 +728,20 @@ multiclass VPatBinaryFPVL_VV_VF<SDPatternOperator vop, string instruction_name>
}
}
+multiclass VPatBinaryFPVL_VV_VF_E<SDPatternOperator vop,
+ string instruction_name> {
+ foreach vti = AllFloatVectors in {
+ defm : VPatBinaryVL_V_E<vop, instruction_name, "VV",
+ vti.Vector, vti.Vector, vti.Vector, vti.Mask,
+ vti.Log2SEW, vti.LMul, vti.SEW,
+ vti.RegClass, vti.RegClass, vti.RegClass>;
+ defm : VPatBinaryVL_VF_E<vop, instruction_name#"_V"#vti.ScalarSuffix,
+ vti.Vector, vti.Vector, vti.Mask, vti.Log2SEW,
+ vti.LMul, vti.SEW, vti.RegClass, vti.RegClass,
+ vti.ScalarRegClass>;
+ }
+}
+
multiclass VPatBinaryFPVL_R_VF<SDPatternOperator vop, string instruction_name> {
foreach fvti = AllFloatVectors in {
def : Pat<(fvti.Vector (vop (SplatFPOp fvti.ScalarRegClass:$rs2),
@@ -652,6 +756,21 @@ multiclass VPatBinaryFPVL_R_VF<SDPatternOperator vop, string instruction_name> {
}
}
+multiclass VPatBinaryFPVL_R_VF_E<SDPatternOperator vop,
+ string instruction_name> {
+ foreach fvti = AllFloatVectors in {
+ def : Pat<(fvti.Vector (vop (SplatFPOp fvti.ScalarRegClass:$rs2),
+ fvti.RegClass:$rs1,
+ (fvti.Vector fvti.RegClass:$merge),
+ (fvti.Mask V0),
+ VLOpFrag)),
+ (!cast<Instruction>(instruction_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX#"_E"#fvti.SEW#"_MASK")
+ fvti.RegClass:$merge,
+ fvti.RegClass:$rs1, fvti.ScalarRegClass:$rs2,
+ (fvti.Mask V0), GPR:$vl, fvti.Log2SEW, TAIL_AGNOSTIC)>;
+ }
+}
+
multiclass VPatIntegerSetCCVL_VV<VTypeInfo vti, string instruction_name,
CondCode cc> {
def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1),
@@ -1511,10 +1630,10 @@ defm : VPatBinaryVL_VV_VX<riscv_mulhs_vl, "PseudoVMULH">;
defm : VPatBinaryVL_VV_VX<riscv_mulhu_vl, "PseudoVMULHU">;
// 11.11. Vector Integer Divide Instructions
-defm : VPatBinaryVL_VV_VX<riscv_udiv_vl, "PseudoVDIVU">;
-defm : VPatBinaryVL_VV_VX<riscv_sdiv_vl, "PseudoVDIV">;
-defm : VPatBinaryVL_VV_VX<riscv_urem_vl, "PseudoVREMU">;
-defm : VPatBinaryVL_VV_VX<riscv_srem_vl, "PseudoVREM">;
+defm : VPatBinaryVL_VV_VX_E<riscv_udiv_vl, "PseudoVDIVU">;
+defm : VPatBinaryVL_VV_VX_E<riscv_sdiv_vl, "PseudoVDIV">;
+defm : VPatBinaryVL_VV_VX_E<riscv_urem_vl, "PseudoVREMU">;
+defm : VPatBinaryVL_VV_VX_E<riscv_srem_vl, "PseudoVREM">;
// 11.12. Vector Widening Integer Multiply Instructions
defm : VPatBinaryWVL_VV_VX<riscv_vwmul_vl, "PseudoVWMUL">;
@@ -1640,8 +1759,8 @@ defm : VPatWidenBinaryFPVL_VV_VF_WV_WF<riscv_fsub_vl, "PseudoVFWSUB">;
// 13.4. Vector Single-Width Floating-Point Multiply/Divide Instructions
defm : VPatBinaryFPVL_VV_VF<any_riscv_fmul_vl, "PseudoVFMUL">;
-defm : VPatBinaryFPVL_VV_VF<any_riscv_fdiv_vl, "PseudoVFDIV">;
-defm : VPatBinaryFPVL_R_VF<any_riscv_fdiv_vl, "PseudoVFRDIV">;
+defm : VPatBinaryFPVL_VV_VF_E<any_riscv_fdiv_vl, "PseudoVFDIV">;
+defm : VPatBinaryFPVL_R_VF_E<any_riscv_fdiv_vl, "PseudoVFRDIV">;
// 13.5. Vector Widening Floating-Point Multiply Instructions
defm : VPatWidenBinaryFPVL_VV_VF<riscv_fmul_vl, riscv_fpextend_vl_oneuse, "PseudoVFWMUL">;
diff --git a/llvm/lib/Target/RISCV/RISCVScheduleV.td b/llvm/lib/Target/RISCV/RISCVScheduleV.td
index 0bb9279bf6bc..6c0a04a153be 100644
--- a/llvm/lib/Target/RISCV/RISCVScheduleV.td
+++ b/llvm/lib/Target/RISCV/RISCVScheduleV.td
@@ -247,8 +247,8 @@ defm "" : LMULSchedWrites<"WriteVICmpI">;
defm "" : LMULSchedWrites<"WriteVIMulV">;
defm "" : LMULSchedWrites<"WriteVIMulX">;
// 11.11. Vector Integer Divide Instructions
-defm "" : LMULSchedWrites<"WriteVIDivV">;
-defm "" : LMULSchedWrites<"WriteVIDivX">;
+defm "" : LMULSEWSchedWrites<"WriteVIDivV">;
+defm "" : LMULSEWSchedWrites<"WriteVIDivX">;
// 11.12. Vector Widening Integer Multiply Instructions
defm "" : LMULSchedWritesW<"WriteVIWMulV">;
defm "" : LMULSchedWritesW<"WriteVIWMulX">;
@@ -297,8 +297,8 @@ defm "" : LMULSchedWritesFW<"WriteVFWALUF">;
// 13.4. Vector Single-Width Floating-Point Multiply/Divide Instructions
defm "" : LMULSchedWrites<"WriteVFMulV">;
defm "" : LMULSchedWrites<"WriteVFMulF">;
-defm "" : LMULSchedWrites<"WriteVFDivV">;
-defm "" : LMULSchedWrites<"WriteVFDivF">;
+defm "" : LMULSEWSchedWrites<"WriteVFDivV">;
+defm "" : LMULSEWSchedWrites<"WriteVFDivF">;
// 13.5. Vector Widening Floating-Point Multiply
defm "" : LMULSchedWritesFW<"WriteVFWMulV">;
defm "" : LMULSchedWritesFW<"WriteVFWMulF">;
@@ -471,8 +471,8 @@ defm "" : LMULSchedReads<"ReadVICmpX">;
defm "" : LMULSchedReads<"ReadVIMulV">;
defm "" : LMULSchedReads<"ReadVIMulX">;
// 11.11. Vector Integer Divide Instructions
-defm "" : LMULSchedReads<"ReadVIDivV">;
-defm "" : LMULSchedReads<"ReadVIDivX">;
+defm "" : LMULSEWSchedReads<"ReadVIDivV">;
+defm "" : LMULSEWSchedReads<"ReadVIDivX">;
// 11.12. Vector Widening Integer Multiply Instructions
defm "" : LMULSchedReadsW<"ReadVIWMulV">;
defm "" : LMULSchedReadsW<"ReadVIWMulX">;
@@ -516,8 +516,8 @@ defm "" : LMULSchedReadsFW<"ReadVFWALUF">;
// 13.4. Vector Single-Width Floating-Point Multiply/Divide Instructions
defm "" : LMULSchedReads<"ReadVFMulV">;
defm "" : LMULSchedReads<"ReadVFMulF">;
-defm "" : LMULSchedReads<"ReadVFDivV">;
-defm "" : LMULSchedReads<"ReadVFDivF">;
+defm "" : LMULSEWSchedReads<"ReadVFDivV">;
+defm "" : LMULSEWSchedReads<"ReadVFDivF">;
// 13.5. Vector Widening Floating-Point Multiply
defm "" : LMULSchedReadsFW<"ReadVFWMulV">;
defm "" : LMULSchedReadsFW<"ReadVFWMulF">;
@@ -712,8 +712,8 @@ defm "" : LMULWriteRes<"WriteVICmpX", []>;
defm "" : LMULWriteRes<"WriteVICmpI", []>;
defm "" : LMULWriteRes<"WriteVIMulV", []>;
defm "" : LMULWriteRes<"WriteVIMulX", []>;
-defm "" : LMULWriteRes<"WriteVIDivV", []>;
-defm "" : LMULWriteRes<"WriteVIDivX", []>;
+defm "" : LMULSEWWriteRes<"WriteVIDivV", []>;
+defm "" : LMULSEWWriteRes<"WriteVIDivX", []>;
defm "" : LMULWriteResW<"WriteVIWMulV", []>;
defm "" : LMULWriteResW<"WriteVIWMulX", []>;
defm "" : LMULWriteRes<"WriteVIMulAddV", []>;
@@ -749,8 +749,8 @@ defm "" : LMULWriteResFW<"WriteVFWALUV", []>;
defm "" : LMULWriteResFW<"WriteVFWALUF", []>;
defm "" : LMULWriteRes<"WriteVFMulV", []>;
defm "" : LMULWriteRes<"WriteVFMulF", []>;
-defm "" : LMULWriteRes<"WriteVFDivV", []>;
-defm "" : LMULWriteRes<"WriteVFDivF", []>;
+defm "" : LMULSEWWriteRes<"WriteVFDivV", []>;
+defm "" : LMULSEWWriteRes<"WriteVFDivF", []>;
defm "" : LMULWriteResFW<"WriteVFWMulV", []>;
defm "" : LMULWriteResFW<"WriteVFWMulF", []>;
defm "" : LMULWriteRes<"WriteVFMulAddV", []>;
@@ -867,8 +867,8 @@ defm "" : LMULReadAdvance<"ReadVICmpV", 0>;
defm "" : LMULReadAdvance<"ReadVICmpX", 0>;
defm "" : LMULReadAdvance<"ReadVIMulV", 0>;
defm "" : LMULReadAdvance<"ReadVIMulX", 0>;
-defm "" : LMULReadAdvance<"ReadVIDivV", 0>;
-defm "" : LMULReadAdvance<"ReadVIDivX", 0>;
+defm "" : LMULSEWReadAdvance<"ReadVIDivV", 0>;
+defm "" : LMULSEWReadAdvance<"ReadVIDivX", 0>;
defm "" : LMULReadAdvanceW<"ReadVIWMulV", 0>;
defm "" : LMULReadAdvanceW<"ReadVIWMulX", 0>;
defm "" : LMULReadAdvance<"ReadVIMulAddV", 0>;
@@ -899,8 +899,8 @@ defm "" : LMULReadAdvanceFW<"ReadVFWALUV", 0>;
defm "" : LMULReadAdvanceFW<"ReadVFWALUF", 0>;
defm "" : LMULReadAdvance<"ReadVFMulV", 0>;
defm "" : LMULReadAdvance<"ReadVFMulF", 0>;
-defm "" : LMULReadAdvance<"ReadVFDivV", 0>;
-defm "" : LMULReadAdvance<"ReadVFDivF", 0>;
+defm "" : LMULSEWReadAdvance<"ReadVFDivV", 0>;
+defm "" : LMULSEWReadAdvance<"ReadVFDivF", 0>;
defm "" : LMULReadAdvanceFW<"ReadVFWMulV", 0>;
defm "" : LMULReadAdvanceFW<"ReadVFWMulF", 0>;
defm "" : LMULReadAdvance<"ReadVFMulAddV", 0>;
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