[llvm] 5ab9ae1 - [RISCV] Made vrgather.vv and vrgatherei16 pseudoinstructions SEW-aware
Nitin John Raj via llvm-commits
llvm-commits at lists.llvm.org
Fri Mar 24 16:41:05 PDT 2023
Author: Nitin John Raj
Date: 2023-03-24T16:33:24-07:00
New Revision: 5ab9ae12b703647d2482e71b0a98158ef3a41dea
URL: https://github.com/llvm/llvm-project/commit/5ab9ae12b703647d2482e71b0a98158ef3a41dea
DIFF: https://github.com/llvm/llvm-project/commit/5ab9ae12b703647d2482e71b0a98158ef3a41dea.diff
LOG: [RISCV] Made vrgather.vv and vrgatherei16 pseudoinstructions SEW-aware
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
llvm/lib/Target/RISCV/RISCVScheduleV.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index 91390fd16d7e..c385224a86c9 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -1939,6 +1939,24 @@ multiclass VPseudoBinary<VReg RetClass,
}
}
+multiclass VPseudoBinary_E<VReg RetClass,
+ VReg Op1Class,
+ DAGOperand Op2Class,
+ LMULInfo MInfo,
+ int sew,
+ string Constraint = ""> {
+ let VLMul = MInfo.value in {
+ defvar suffix = "_" # MInfo.MX # "_E" # sew;
+ def suffix : VPseudoBinaryNoMask<RetClass, Op1Class, Op2Class,
+ Constraint>;
+ def suffix # "_TU" : VPseudoBinaryNoMaskTU<RetClass, Op1Class, Op2Class,
+ Constraint>;
+ def suffix # "_MASK" : VPseudoBinaryMaskPolicy<RetClass, Op1Class, Op2Class,
+ Constraint>,
+ RISCVMaskedPseudo</*MaskOpIdx*/ 3>;
+ }
+}
+
multiclass VPseudoBinaryM<VReg RetClass,
VReg Op1Class,
DAGOperand Op2Class,
@@ -1971,6 +1989,25 @@ multiclass VPseudoBinaryEmul<VReg RetClass,
}
}
+multiclass VPseudoBinaryEmul_E<VReg RetClass,
+ VReg Op1Class,
+ DAGOperand Op2Class,
+ LMULInfo lmul,
+ int sew,
+ LMULInfo emul,
+ string Constraint = ""> {
+ let VLMul = lmul.value in {
+ defvar suffix = "_" # lmul.MX # "_E" # sew # "_" # emul.MX;
+ def suffix : VPseudoBinaryNoMask<RetClass, Op1Class, Op2Class,
+ Constraint>;
+ def suffix # "_TU" : VPseudoBinaryNoMaskTU<RetClass, Op1Class, Op2Class,
+ Constraint>;
+ def suffix # "_MASK" : VPseudoBinaryMaskPolicy<RetClass, Op1Class, Op2Class,
+ Constraint>,
+ RISCVMaskedPseudo</*MaskOpIdx*/ 3>;
+ }
+}
+
multiclass VPseudoTiedBinary<VReg RetClass,
DAGOperand Op2Class,
LMULInfo MInfo,
@@ -1987,6 +2024,10 @@ multiclass VPseudoBinaryV_VV<LMULInfo m, string Constraint = ""> {
defm _VV : VPseudoBinary<m.vrclass, m.vrclass, m.vrclass, m, Constraint>;
}
+multiclass VPseudoBinaryV_VV_E<LMULInfo m, int sew, string Constraint = ""> {
+ defm _VV : VPseudoBinary_E<m.vrclass, m.vrclass, m.vrclass, m, sew, Constraint>;
+}
+
// Similar to VPseudoBinaryV_VV, but uses MxListF.
multiclass VPseudoBinaryFV_VV<LMULInfo m, string Constraint = ""> {
defm _VV : VPseudoBinary<m.vrclass, m.vrclass, m.vrclass, m, Constraint>;
@@ -1995,10 +2036,6 @@ multiclass VPseudoBinaryFV_VV<LMULInfo m, string Constraint = ""> {
multiclass VPseudoVGTR_VV_EEW<int eew, string Constraint = ""> {
foreach m = MxList in {
defvar mx = m.MX;
- defvar WriteVRGatherVV_MX = !cast<SchedWrite>("WriteVRGatherVV_" # mx);
- defvar ReadVRGatherVV_data_MX = !cast<SchedRead>("ReadVRGatherVV_data_" # mx);
- defvar ReadVRGatherVV_index_MX = !cast<SchedRead>("ReadVRGatherVV_index_" # mx);
-
foreach sew = EEWList in {
defvar octuple_lmul = m.octuple;
// emul = lmul * eew / sew
@@ -2006,9 +2043,14 @@ multiclass VPseudoVGTR_VV_EEW<int eew, string Constraint = ""> {
if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then {
defvar emulMX = octuple_to_str<octuple_emul>.ret;
defvar emul = !cast<LMULInfo>("V_" # emulMX);
- defm _VV : VPseudoBinaryEmul<m.vrclass, m.vrclass, emul.vrclass, m, emul, Constraint>,
- Sched<[WriteVRGatherVV_MX, ReadVRGatherVV_data_MX,
- ReadVRGatherVV_index_MX]>;
+ defvar sews = SchedSEWSet<mx>.val;
+ foreach e = sews in {
+ defvar WriteVRGatherVV_MX_E = !cast<SchedWrite>("WriteVRGatherVV_" # mx # "_E" # e);
+ defvar ReadVRGatherVV_data_MX_E = !cast<SchedRead>("ReadVRGatherVV_data_" # mx # "_E" # e);
+ defvar ReadVRGatherVV_index_MX_E = !cast<SchedRead>("ReadVRGatherVV_index_" # mx # "_E" # e);
+ defm _VV : VPseudoBinaryEmul_E<m.vrclass, m.vrclass, emul.vrclass, m, e, emul, Constraint>,
+ Sched<[WriteVRGatherVV_MX_E, ReadVRGatherVV_data_MX_E, ReadVRGatherVV_index_MX_E]>;
+ }
}
}
}
@@ -2404,23 +2446,27 @@ multiclass VPseudoBinaryM_VI<LMULInfo m> {
multiclass VPseudoVGTR_VV_VX_VI<Operand ImmType = simm5, string Constraint = ""> {
foreach m = MxList in {
defvar mx = m.MX;
- defvar WriteVRGatherVV_MX = !cast<SchedWrite>("WriteVRGatherVV_" # mx);
defvar WriteVRGatherVX_MX = !cast<SchedWrite>("WriteVRGatherVX_" # mx);
defvar WriteVRGatherVI_MX = !cast<SchedWrite>("WriteVRGatherVI_" # mx);
- defvar ReadVRGatherVV_data_MX = !cast<SchedRead>("ReadVRGatherVV_data_" # mx);
- defvar ReadVRGatherVV_index_MX = !cast<SchedRead>("ReadVRGatherVV_index_" # mx);
defvar ReadVRGatherVX_data_MX = !cast<SchedRead>("ReadVRGatherVX_data_" # mx);
defvar ReadVRGatherVX_index_MX = !cast<SchedRead>("ReadVRGatherVX_index_" # mx);
defvar ReadVRGatherVI_data_MX = !cast<SchedRead>("ReadVRGatherVI_data_" # mx);
- defm "" : VPseudoBinaryV_VV<m, Constraint>,
- Sched<[WriteVRGatherVV_MX, ReadVRGatherVV_data_MX,
- ReadVRGatherVV_index_MX, ReadVMask]>;
defm "" : VPseudoBinaryV_VX<m, Constraint>,
Sched<[WriteVRGatherVX_MX, ReadVRGatherVX_data_MX,
ReadVRGatherVX_index_MX, ReadVMask]>;
defm "" : VPseudoBinaryV_VI<ImmType, m, Constraint>,
Sched<[WriteVRGatherVI_MX, ReadVRGatherVI_data_MX, ReadVMask]>;
+
+ defvar sews = SchedSEWSet<mx>.val;
+ foreach e = sews in {
+ defvar WriteVRGatherVV_MX_E = !cast<SchedWrite>("WriteVRGatherVV_" # mx # "_E" # e);
+ defvar ReadVRGatherVV_data_MX_E = !cast<SchedRead>("ReadVRGatherVV_data_" # mx # "_E" # e);
+ defvar ReadVRGatherVV_index_MX_E = !cast<SchedRead>("ReadVRGatherVV_index_" # mx # "_E" # e);
+ defm "" : VPseudoBinaryV_VV_E<m, e, Constraint>,
+ Sched<[WriteVRGatherVV_MX_E, ReadVRGatherVV_data_MX_E,
+ ReadVRGatherVV_index_MX_E, ReadVMask]>;
+ }
}
}
@@ -4457,18 +4503,19 @@ multiclass VPatBinaryV_VV<string intrinsic, string instruction,
vti.RegClass, vti.RegClass>;
}
-multiclass VPatBinaryV_VV_INT<string intrinsic, string instruction,
+multiclass VPatBinaryV_VV_INT_E<string intrinsic, string instruction,
list<VTypeInfo> vtilist> {
foreach vti = vtilist in {
defvar ivti = GetIntVTypeInfo<vti>.Vti;
- defm : VPatBinaryTA<intrinsic, instruction # "_VV_" # vti.LMul.MX,
+ defm : VPatBinaryTA<intrinsic,
+ instruction # "_VV_" # vti.LMul.MX # "_E" # vti.SEW,
vti.Vector, vti.Vector, ivti.Vector, vti.Mask,
vti.Log2SEW, vti.RegClass,
vti.RegClass, vti.RegClass>;
}
}
-multiclass VPatBinaryV_VV_INT_EEW<string intrinsic, string instruction,
+multiclass VPatBinaryV_VV_INT_E_EEW<string intrinsic, string instruction,
int eew, list<VTypeInfo> vtilist> {
foreach vti = vtilist in {
// emul = lmul * eew / sew
@@ -4478,7 +4525,7 @@ multiclass VPatBinaryV_VV_INT_EEW<string intrinsic, string instruction,
if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then {
defvar emul_str = octuple_to_str<octuple_emul>.ret;
defvar ivti = !cast<VTypeInfo>("VI" # eew # emul_str);
- defvar inst = instruction # "_VV_" # vti.LMul.MX # "_" # emul_str;
+ defvar inst = instruction # "_VV_" # vti.LMul.MX # "_E" # vti.SEW # "_" # emul_str;
defm : VPatBinaryTA<intrinsic, inst,
vti.Vector, vti.Vector, ivti.Vector, vti.Mask,
vti.Log2SEW, vti.RegClass,
@@ -4967,7 +5014,7 @@ multiclass VPatBinaryM_VX_VI<string intrinsic, string instruction,
multiclass VPatBinaryV_VV_VX_VI_INT<string intrinsic, string instruction,
list<VTypeInfo> vtilist, Operand ImmType = simm5>
- : VPatBinaryV_VV_INT<intrinsic#"_vv", instruction, vtilist>,
+ : VPatBinaryV_VV_INT_E<intrinsic#"_vv", instruction, vtilist>,
VPatBinaryV_VX_INT<intrinsic#"_vx", instruction, vtilist>,
VPatBinaryV_VI<intrinsic#"_vx", instruction, vtilist, ImmType>;
@@ -6455,14 +6502,14 @@ let Predicates = [HasVInstructionsAnyF] in {
let Predicates = [HasVInstructions] in {
defm : VPatBinaryV_VV_VX_VI_INT<"int_riscv_vrgather", "PseudoVRGATHER",
AllIntegerVectors, uimm5>;
- defm : VPatBinaryV_VV_INT_EEW<"int_riscv_vrgatherei16_vv", "PseudoVRGATHEREI16",
+ defm : VPatBinaryV_VV_INT_E_EEW<"int_riscv_vrgatherei16_vv", "PseudoVRGATHEREI16",
/* eew */ 16, AllIntegerVectors>;
} // Predicates = [HasVInstructions]
let Predicates = [HasVInstructionsAnyF] in {
defm : VPatBinaryV_VV_VX_VI_INT<"int_riscv_vrgather", "PseudoVRGATHER",
AllFloatVectors, uimm5>;
- defm : VPatBinaryV_VV_INT_EEW<"int_riscv_vrgatherei16_vv", "PseudoVRGATHEREI16",
+ defm : VPatBinaryV_VV_INT_E_EEW<"int_riscv_vrgatherei16_vv", "PseudoVRGATHEREI16",
/* eew */ 16, AllFloatVectors>;
} // Predicates = [HasVInstructionsAnyF]
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
index 5087628749cb..bca0511c98a3 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
@@ -2047,7 +2047,7 @@ foreach vti = AllIntegerVectors in {
vti.RegClass:$merge,
(vti.Mask V0),
VLOpFrag)),
- (!cast<Instruction>("PseudoVRGATHER_VV_"# vti.LMul.MX#"_MASK")
+ (!cast<Instruction>("PseudoVRGATHER_VV_"# vti.LMul.MX#"_E"# vti.SEW#"_MASK")
vti.RegClass:$merge, vti.RegClass:$rs2, vti.RegClass:$rs1,
(vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
def : Pat<(vti.Vector (riscv_vrgather_vx_vl vti.RegClass:$rs2, GPR:$rs1,
@@ -2073,7 +2073,7 @@ foreach vti = AllIntegerVectors in {
if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then {
defvar emul_str = octuple_to_str<octuple_emul>.ret;
defvar ivti = !cast<VTypeInfo>("VI16" # emul_str);
- defvar inst = "PseudoVRGATHEREI16_VV_" # vti.LMul.MX # "_" # emul_str;
+ defvar inst = "PseudoVRGATHEREI16_VV_" # vti.LMul.MX # "_E" # vti.SEW # "_" # emul_str;
def : Pat<(vti.Vector
(riscv_vrgatherei16_vv_vl vti.RegClass:$rs2,
@@ -2117,7 +2117,7 @@ foreach vti = AllFloatVectors in {
vti.RegClass:$merge,
(vti.Mask V0),
VLOpFrag)),
- (!cast<Instruction>("PseudoVRGATHER_VV_"# vti.LMul.MX#"_MASK")
+ (!cast<Instruction>("PseudoVRGATHER_VV_"# vti.LMul.MX#"_E"# vti.SEW#"_MASK")
vti.RegClass:$merge, vti.RegClass:$rs2, vti.RegClass:$rs1,
(vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
def : Pat<(vti.Vector (riscv_vrgather_vx_vl vti.RegClass:$rs2, GPR:$rs1,
@@ -2143,7 +2143,7 @@ foreach vti = AllFloatVectors in {
if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then {
defvar emul_str = octuple_to_str<octuple_emul>.ret;
defvar ivti = !cast<VTypeInfo>("VI16" # emul_str);
- defvar inst = "PseudoVRGATHEREI16_VV_" # vti.LMul.MX # "_" # emul_str;
+ defvar inst = "PseudoVRGATHEREI16_VV_" # vti.LMul.MX # "_E" # vti.SEW # "_" # emul_str;
def : Pat<(vti.Vector
(riscv_vrgatherei16_vv_vl vti.RegClass:$rs2,
diff --git a/llvm/lib/Target/RISCV/RISCVScheduleV.td b/llvm/lib/Target/RISCV/RISCVScheduleV.td
index 44c7b9b0127b..0bb9279bf6bc 100644
--- a/llvm/lib/Target/RISCV/RISCVScheduleV.td
+++ b/llvm/lib/Target/RISCV/RISCVScheduleV.td
@@ -383,7 +383,7 @@ defm "" : LMULSchedWrites<"WriteVISlideI">;
defm "" : LMULSchedWrites<"WriteVISlide1X">;
defm "" : LMULSchedWrites<"WriteVFSlide1F">;
// 16.4. Vector Register Gather Instructions
-defm "" : LMULSchedWrites<"WriteVRGatherVV">;
+defm "" : LMULSEWSchedWrites<"WriteVRGatherVV">;
defm "" : LMULSchedWrites<"WriteVRGatherVX">;
defm "" : LMULSchedWrites<"WriteVRGatherVI">;
// 16.5. Vector Compress Instruction
@@ -605,8 +605,8 @@ defm "" : LMULSchedReads<"ReadVISlideX">;
defm "" : LMULSchedReads<"ReadVFSlideV">;
defm "" : LMULSchedReads<"ReadVFSlideF">;
// 16.4. Vector Register Gather Instructions
-defm "" : LMULSchedReads<"ReadVRGatherVV_data">;
-defm "" : LMULSchedReads<"ReadVRGatherVV_index">;
+defm "" : LMULSEWSchedReads<"ReadVRGatherVV_data">;
+defm "" : LMULSEWSchedReads<"ReadVRGatherVV_index">;
defm "" : LMULSchedReads<"ReadVRGatherVX_data">;
defm "" : LMULSchedReads<"ReadVRGatherVX_index">;
defm "" : LMULSchedReads<"ReadVRGatherVI_data">;
@@ -800,7 +800,7 @@ defm "" : LMULWriteRes<"WriteVISlideX", []>;
defm "" : LMULWriteRes<"WriteVISlideI", []>;
defm "" : LMULWriteRes<"WriteVISlide1X", []>;
defm "" : LMULWriteRes<"WriteVFSlide1F", []>;
-defm "" : LMULWriteRes<"WriteVRGatherVV", []>;
+defm "" : LMULSEWWriteRes<"WriteVRGatherVV", []>;
defm "" : LMULWriteRes<"WriteVRGatherVX", []>;
defm "" : LMULWriteRes<"WriteVRGatherVI", []>;
defm "" : LMULSEWWriteRes<"WriteVCompressV", []>;
@@ -958,13 +958,12 @@ defm "" : LMULReadAdvance<"ReadVISlideV", 0>;
defm "" : LMULReadAdvance<"ReadVISlideX", 0>;
defm "" : LMULReadAdvance<"ReadVFSlideV", 0>;
defm "" : LMULReadAdvance<"ReadVFSlideF", 0>;
-defm "" : LMULReadAdvance<"ReadVRGatherVV_data", 0>;
-defm "" : LMULReadAdvance<"ReadVRGatherVV_index", 0>;
+defm "" : LMULSEWReadAdvance<"ReadVRGatherVV_data", 0>;
+defm "" : LMULSEWReadAdvance<"ReadVRGatherVV_index", 0>;
defm "" : LMULReadAdvance<"ReadVRGatherVX_data", 0>;
defm "" : LMULReadAdvance<"ReadVRGatherVX_index", 0>;
defm "" : LMULReadAdvance<"ReadVRGatherVI_data", 0>;
defm "" : LMULReadAdvance<"ReadVGatherV", 0>;
-defm "" : LMULReadAdvance<"ReadVGatherX", 0>;
defm "" : LMULSEWReadAdvance<"ReadVCompressV", 0>;
// These are already LMUL aware
def : ReadAdvance<ReadVMov1V, 0>;
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