[PATCH] D146752: [RISCV][RISCVISelLowering] Add tail agnostic policy operand to VECREDUCE instructions

[Nitin John Raj via Phabricator via llvm-commits]

nitinjohnraj updated this revision to Diff 508172.
nitinjohnraj marked 8 inline comments as done.
nitinjohnraj added a comment.

Fixed so that the policy for vecreduce instructions is `ta, ma` + some refactoring


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D146752/new/

https://reviews.llvm.org/D146752

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vfredmax.ll
  llvm/test/CodeGen/RISCV/rvv/vfredmin.ll
  llvm/test/CodeGen/RISCV/rvv/vfredosum.ll
  llvm/test/CodeGen/RISCV/rvv/vfredusum.ll
  llvm/test/CodeGen/RISCV/rvv/vfwredosum.ll
  llvm/test/CodeGen/RISCV/rvv/vfwredusum.ll
  llvm/test/CodeGen/RISCV/rvv/vmv-copy.mir
  llvm/test/CodeGen/RISCV/rvv/vredand-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vredand-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vredmax-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vredmax-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vredmin-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vredmin-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vredminu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vredminu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vredor-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vredor-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vredsum-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vredsum-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vredxor-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vredxor-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir
  llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
  llvm/test/CodeGen/RISCV/rvv/vwredsum-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vwredsum-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vwredsumu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vwredsumu-rv64.ll