[PATCH] D146626: [RISCV] Add test case for combining vrgather
Philip Reames via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Mar 22 07:55:03 PDT 2023
reames requested changes to this revision.
reames added inline comments.
This revision now requires changes to proceed.
================
Comment at: llvm/test/CodeGen/RISCV/rvv/combine-gather.ll:19
+; CHECK-NEXT: ret
+ %res = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
+ ret <8 x i8> %res
----------------
Please add a couple more tests where the result is not a concat. A few ideas:
0,1,2,3,0,1,2,3
0,1,2,3,11,10,9,8
0,1,2,3,12,13,14,15
0,1,2,3, 8,11,10,9
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D146626/new/
https://reviews.llvm.org/D146626
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