[PATCH] D146626: [RISCV] Add test case for combining vrgather

[Luke Lau via Phabricator via llvm-commits]

luke created this revision.
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Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D146626

Files:
  llvm/test/CodeGen/RISCV/rvv/combine-gather.ll


Index: llvm/test/CodeGen/RISCV/rvv/combine-gather.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rvv/combine-gather.ll
@@ -0,0 +1,21 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc -mtriple=riscv32 -mattr=+v < %s | FileCheck %s
+; RUN: llc -mtriple=riscv64 -mattr=+v < %s | FileCheck %s
+
+; FIXME: There should only be one vrgather here
+
+define <8 x i8> @gather_i8(<8 x i8> %v, <8 x i8> %w) {
+; CHECK-LABEL: gather_i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
+; CHECK-NEXT:    vid.v v11
+; CHECK-NEXT:    vrgather.vv v10, v8, v11
+; CHECK-NEXT:    li a0, 240
+; CHECK-NEXT:    vmv.s.x v0, a0
+; CHECK-NEXT:    vadd.vi v8, v11, -4
+; CHECK-NEXT:    vrgather.vv v10, v9, v8, v0.t
+; CHECK-NEXT:    vmv1r.v v8, v10
+; CHECK-NEXT:    ret
+  %res = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
+  ret <8 x i8> %res
+}


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