[PATCH] D146522: [RISCV] Model vlseg/vsseg in interleaved memory ops

[Luke Lau via Phabricator via llvm-commits]

luke added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp:394-396
+      auto *LegalFVTy = FixedVectorType::get(FVTy->getElementType(),
+                                             LT.second.getVectorNumElements());
+      if (TLI->isLegalInterleavedAccessType(LegalFVTy, Factor, DL)) {
----------------
If we just use the un-legalized type to cost model, then interleaves of `<6 x i8>` etc. which are common with Factor=3 are reported as really expensive, when in fact they can be selected as vlseg/vsseg.
Perhaps there's a better way to account for this though: I was surprised that getMemoryOpCost reported such a high cost (num elements + 1) for these types.


Repository:
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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D146522/new/

https://reviews.llvm.org/D146522