[PATCH] D146522: [RISCV] Model vlseg/vsseg in interleaved memory ops

[Luke Lau via Phabricator via llvm-commits]

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If the legalized type is a legal interleaved access type (i.e. there's a
supported vlseg/vsseg instruction for it), the interleaved access pass
will pick any interleaved memory op (wide load + shuffles) and lower it
into a vlseg/vsseg intrinsic.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D146522

Files:
  llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
  llvm/test/Transforms/LoopVectorize/RISCV/interleaved-accesses.ll
  llvm/test/Transforms/LoopVectorize/RISCV/interleaved-cost.ll

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