[PATCH] D146121: [DAG] Move lshr narrowing from visitANDLike to SimplifyDemandedBits (WIP)

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


================
Comment at: llvm/test/CodeGen/X86/bswap.ll:171
+; CHECK64-NEXT:    shrl $8, %ecx
 ; CHECK64-NEXT:    shlq $8, %rax
 ; CHECK64-NEXT:    orq %rcx, %rax
----------------
Looks like an equivalent patch for shl narrowing would be useful


================
Comment at: llvm/test/CodeGen/X86/bswap.ll:232
+; CHECK64-NEXT:    shlq $8, %rax
+; CHECK64-NEXT:    orq %rcx, %rax
 ; CHECK64-NEXT:    retq
----------------
Not sure if shl narrowing would solve this or we need better zext/trunc handling in the bswap matcher


================
Comment at: llvm/test/CodeGen/X86/h-register-addressing-64.ll:67
+; CHECK-NEXT:    andl $2040, %esi # imm = 0x7F8
+; CHECK-NEXT:    movzbl (%rdi,%rsi), %eax
 ; CHECK-NEXT:    retq
----------------
Regression (WIP)


================
Comment at: llvm/test/CodeGen/X86/h-register-addressing-64.ll:81
+; CHECK-NEXT:    andl $1020, %esi # imm = 0x3FC
+; CHECK-NEXT:    movzbl (%rdi,%rsi), %eax
 ; CHECK-NEXT:    retq
----------------
Regression (WIP)


================
Comment at: llvm/test/CodeGen/X86/h-register-addressing-64.ll:95
+; CHECK-NEXT:    andl $510, %esi # imm = 0x1FE
+; CHECK-NEXT:    movzbl (%rdi,%rsi), %eax
 ; CHECK-NEXT:    retq
----------------
Regression (WIP)


================
Comment at: llvm/test/CodeGen/X86/illegal-bitfield-loadstore.ll:119
+; X64-NEXT:    movzbl 6(%rdi), %ecx
+; X64-NEXT:    movb %cl, 6(%rdi)
 ; X64-NEXT:    movw %ax, 4(%rdi)
----------------
Regression (WIP) - dead store folds might fail on load-ext / store-trunc mixtures?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D146121/new/

https://reviews.llvm.org/D146121