[PATCH] D146121: [DAG] Move lshr narrowing from visitANDLike to SimplifyDemandedBits (WIP)

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon created this revision.
RKSimon added reviewers: spatel, nikic, foad, pengfei, goldstein.w.n, kazu.
Herald added subscribers: kosarev, StephenFan, ecnelises, kerbowa, hiraditya, jvesely.
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RKSimon requested review of this revision.
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Inspired by some of the cases from D145468 <https://reviews.llvm.org/D145468>

Let SimplifyDemandedBits to drive the narrowing of lshr to half-width if we don't require the upper bits, the narrowed shift is profitable and the zext/trunc are free.

There's still a number of regressions that I'm looking at, but the general shape of the patch is ready for initial review.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D146121

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/test/CodeGen/AMDGPU/idot4s.ll
  llvm/test/CodeGen/AMDGPU/idot4u.ll
  llvm/test/CodeGen/AMDGPU/idot8s.ll
  llvm/test/CodeGen/AMDGPU/idot8u.ll
  llvm/test/CodeGen/AMDGPU/partial-shift-shrink.ll
  llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
  llvm/test/CodeGen/AMDGPU/shift-i128.ll
  llvm/test/CodeGen/AMDGPU/wave32.ll
  llvm/test/CodeGen/X86/2008-05-12-tailmerge-5.ll
  llvm/test/CodeGen/X86/2009-05-30-ISelBug.ll
  llvm/test/CodeGen/X86/2011-10-19-LegelizeLoad.ll
  llvm/test/CodeGen/X86/3addr-or.ll
  llvm/test/CodeGen/X86/and-shift.ll
  llvm/test/CodeGen/X86/bswap.ll
  llvm/test/CodeGen/X86/combine-bitreverse.ll
  llvm/test/CodeGen/X86/const-shift-of-constmasked.ll
  llvm/test/CodeGen/X86/extract-bits.ll
  llvm/test/CodeGen/X86/h-register-addressing-64.ll
  llvm/test/CodeGen/X86/h-registers-0.ll
  llvm/test/CodeGen/X86/illegal-bitfield-loadstore.ll
  llvm/test/CodeGen/X86/lzcnt-cmp.ll
  llvm/test/CodeGen/X86/zext-logicop-shift-load.ll

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