[PATCH] D145155: [RISCV] Enable interleaved access vectorization

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp:413
+
+  assert(Opcode == Instruction::Store && "Opcode must be load or store");
+  // For an interleaving load of 2 vectors, we perform one large interleaving
----------------
"Opcode must be a store"?


================
Comment at: llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp:414
+  assert(Opcode == Instruction::Store && "Opcode must be load or store");
+  // For an interleaving load of 2 vectors, we perform one large interleaving
+  // shuffle that goes into the wide store
----------------
load -> store?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D145155/new/

https://reviews.llvm.org/D145155