[PATCH] D145943: [AArchExpandPseudo] Preserve instruction debug number in expansions

[Felipe de Azevedo Piovezan via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGdde08c9c4856: [AArchExpandPseudo] Preserve instruction debug number in expansions (authored by fdeazeve).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D145943/new/

https://reviews.llvm.org/D145943

Files:
  llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
  llvm/test/CodeGen/AArch64/expand-subs-pseudo.mir


Index: llvm/test/CodeGen/AArch64/expand-subs-pseudo.mir
===================================================================
--- llvm/test/CodeGen/AArch64/expand-subs-pseudo.mir
+++ llvm/test/CodeGen/AArch64/expand-subs-pseudo.mir
@@ -3,8 +3,8 @@
 ---
 # CHECK-LABEL:  name: test
 # CHECK-LABEL:  bb.0:
-# CHECK:          $w5 = SUBSWrs renamable $w3, renamable $w2, 0, implicit-def dead $nzcv
-# CHECK-NEXT:     $w6 = SUBSWrs renamable $w5, renamable $w3, 0, implicit-def $nzcv
+# CHECK:          $w5 = SUBSWrs renamable $w3, renamable $w2, 0, implicit-def dead $nzcv, debug-instr-number 1
+# CHECK-NEXT:     $w6 = SUBSWrs renamable $w5, renamable $w3, 0, implicit-def $nzcv, debug-instr-number 2
 # CHECK-NEXT:     RET undef $lr
 #
 name:            test
@@ -14,8 +14,8 @@
   bb.0:
     liveins: $w5, $w6, $x2, $x3
 
-    renamable $w5 = nsw SUBSWrr renamable $w3, renamable $w2, implicit-def dead $nzcv
-    renamable $w6 = nsw SUBSWrr renamable $w5, renamable $w3, implicit-def $nzcv
+    renamable $w5 = nsw SUBSWrr renamable $w3, renamable $w2, implicit-def dead $nzcv, debug-instr-number 1
+    renamable $w6 = nsw SUBSWrr renamable $w5, renamable $w3, implicit-def $nzcv, debug-instr-number 2
     RET_ReallyLR
 
 ...
Index: llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
+++ llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
@@ -1177,6 +1177,8 @@
         .add(MI.getOperand(2))
         .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0));
     transferImpOps(MI, MIB1, MIB1);
+    if (auto DebugNumber = MI.peekDebugInstrNum())
+      NewMI->setDebugInstrNum(DebugNumber);
     MI.eraseFromParent();
     return true;
   }


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