[PATCH] D145939: [DAG] Fold multiple insert_vector_elt of zero values into an AND mask

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


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Comment at: llvm/test/CodeGen/X86/clear_upper_vector_element_bits.ll:722
 
 define <32 x i8> @_clearupper32xi8b(<32 x i8>) nounwind {
 ; SSE2-LABEL: _clearupper32xi8b:
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pengfei wrote:
> Are SSE cases getting worse?
Yes - on SSE we have the weird case of an illegal type (32 x i8) being cast to an even more illegal type (64 x i4) - I'm looking at potential fixes.

I added these test cases years ago and they have been a pain ever since :) 


Repository:
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  https://reviews.llvm.org/D145939/new/

https://reviews.llvm.org/D145939