[PATCH] D145930: [X86] Fix encoding for ATOMIC_LOGIC_OP

[Nabeel Omer via Phabricator via llvm-commits]

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In D140939 <https://reviews.llvm.org/D140939> the following issue was introduced:

  multiclass ATOMIC_LOGIC_OP_RM<bits<8> Opc8, string s> {
    let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1,
        SchedRW = [WriteBitTestSetRegRMW]  in {
      def 16rm : Ii8<Opc8, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),           -------> Type Ii8
                    !strconcat(s, "{w}\t{$src2, $src1|$src1, $src2}"),
                    [(set EFLAGS, (!cast<SDNode>("x86_rm_" # s) addr:$src1, GR16:$src2))]>,
                 OpSize16, TB, LOCK;
      def 32rm : Ii8<Opc8, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),           -------> Type Ii8
                    !strconcat(s, "{l}\t{$src2, $src1|$src1, $src2}"),
                    [(set EFLAGS, (!cast<SDNode>("x86_rm_" # s) addr:$src1, GR32:$src2))]>,
                 OpSize32, TB, LOCK;
      def 64rm : RIi8<Opc8, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),         -------> Type RIi8
                     !strconcat(s, "{q}\t{$src2, $src1|$src1, $src2}"),
                     [(set EFLAGS, (!cast<SDNode>("x86_rm_" # s) addr:$src1, GR64:$src2))]>,
                 TB, LOCK;
    }
  }
  
  ...
  
  --- Incorrect base opcodes for 8 bit immediate (https://www.felixcloutier.com/x86/bts. https://www.felixcloutier.com/x86/btc, https://www.felixcloutier.com/x86/btr)
  defm LOCK_BTS_RM : ATOMIC_LOGIC_OP_RM<0xAB, "bts">;
  defm LOCK_BTC_RM : ATOMIC_LOGIC_OP_RM<0xBB, "btc">;
  defm LOCK_BTR_RM : ATOMIC_LOGIC_OP_RM<0xB3, "btr">;

This patch fixes the issue and adds a regression test.

Patch with a failing test coming up.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D145930

Files:
  llvm/lib/Target/X86/X86InstrCompiler.td
  llvm/test/CodeGen/X86/atomic-rm-bit-test-64.ll

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