[PATCH] D145572: [llvm][Uniformity] consistently handle uniform instructions

[Ruiling, Song via Phabricator via llvm-commits]

ruiling added a comment.

> I am not sure what your question is:
>
> 1. Cycle is assumed to be divergent because it is irreducible. But operations that are always uniform need not be assumed to be divergent. That is this case.
> 2. Cycle has divergent exit. Value that is always uniform may still be divergent at its used. That is separately handled by temporal divergence.

I am asking for the second. thanks for the explanation.


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https://reviews.llvm.org/D145572