[PATCH] D144086: [AArch64] Load into zero vector patterns

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

Hi - thanks for the report. It sounds like the offset might be wrong from the look at the assembly. This instructions specifically:

  10534: 40 f4 7f 3d  	ldr	b0, [x2, #4093]
  vs
  10534: 46 0c 00 d1  	sub	x6, x2, #3
  1053c: c0 00 40 0d  	ld1	{ v0.b }[0], [x6]

I think I see the problem - It looks like it should be using an LDUR for those instructions. When printing assembly it will produce an `ldr b0, [x2, -3]` instruction, but emitting obj files gives the large positive offset. I will put a fix in for that issue now.

I've been unable to produce the same output from https://gist.github.com/bjacob/2ed1bce14ae4d67b4261adee70089e29 though - I probably don't know the right set of commands and was just using mlir-translate to convert the file to llvm-ir. Do you know what commands are needed to compile it to assembly?


Repository:
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https://reviews.llvm.org/D144086