[PATCH] D145497: [AArch64] Allocate emergency spillslot when using fixed-length SVE.

[Sander de Smalen via Phabricator via llvm-commits]

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The SVE reg+imm addressing modes require the immediate to be a multiple
of VL. When it is not a multiple of VL, it can use `0` for the immediate
and use an `add` instruction to materialise the base-register.

When using SVE instructions to access fixed-length vectors on the stack
that are not VL-aligned, the frame should anticipate that it might require
an emergency spill-slot to accomodate for an extra 'add' to materialize
the base-address of the load when there are no free registers available.

Fixes https://github.com/llvm/llvm-project/issues/60918


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D145497

Files:
  llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
  llvm/test/CodeGen/AArch64/framelayout-sve-scavengingslot.mir
  llvm/test/CodeGen/AArch64/sve-fixed-ld2-alloca.ll
  llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ld2-alloca.ll

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