[PATCH] D145441: [AMDGPU] Define data layout entries for buffers

[Jay Foad via Phabricator via llvm-commits]

foad added a comment.

Just my 2p: it feels a bit premature to commit patches for this. It feels more like something you could prototype on a branch somewhere and come back when you have more experience with how it all works out in practice.

But I don't actually object to the patch, if the other reviewers are happy and it doens't break anything.

> The first is address space 7, a non-integral address space (which was
> already in the data layout) that has 160-bit pointers (which are
> 256-bit aligned)

Any particular reason for choosing 256-bit alignment?

> However, they must not be used as the arguments to
> getelementptr or otherwise used in address computations

I don't understand what kind of rule this is and how it would be enforced. Is it something that will be written into the IR LangRef?

> This commit also updates the "fallback address space" for buffer
> intrinsics to the buffer resource,

It's not clear to me that this is any more or less correct, since 7 and 8 behave identically wrt alias analysis don't they?


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https://reviews.llvm.org/D145441