[PATCH] D142998: [SVE][codegen] Add few more tests for MUL followed by ADD/SUB (NFC)
Sushant Gokhale via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Mar 6 23:15:55 PST 2023
sushgokh added inline comments.
================
Comment at: llvm/test/CodeGen/AArch64/sve-int-arith.ll:342
+
+define <vscale x 16 x i8> @mla_i8_test1(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) {
+; CHECK-LABEL: mla_i8_test1:
----------------
paulwalker-arm wrote:
> Please name the tests after the expected resulting instruction, so `mad` in this case.
So, I have named it as per the current instruction. Once the pseudo instr generation patch lands, will name as per appropriate instruction. Sounds good?
================
Comment at: llvm/test/CodeGen/AArch64/sve-int-arith.ll:402-403
+ %r1 = add <vscale x 16 x i8> %c, %r0
+ %r2 = add <vscale x 16 x i8> %r1, %a
+ %r3 = add <vscale x 16 x i8> %r2, %b
+ ret <vscale x 16 x i8> %r3
----------------
paulwalker-arm wrote:
> Does simplify the mla tests to:
> ```
> %prod = mul <vscale x 2 x i64> %b, %c
> %res = add <vscale x 2 x i64> %a, %prod
> ret <vscale x 2 x i64> %res
> ```
> give the desired output?
>
Yes, it works. Thanks. WIll update tests.
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D142998/new/
https://reviews.llvm.org/D142998
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