[llvm] 5a3d9e0 - [InstCombine] Transform `(shift X, Or(Y, BitWidth-1))` -> `(shift X,BitWidth-1)`

[Noah Goldstein via llvm-commits]

Author: Noah Goldstein
Date: 2023-03-06T20:30:06-06:00
New Revision: 5a3d9e06170a8a8aadee4a6db1ed61732537d076

URL: https://github.com/llvm/llvm-project/commit/5a3d9e06170a8a8aadee4a6db1ed61732537d076
DIFF: https://github.com/llvm/llvm-project/commit/5a3d9e06170a8a8aadee4a6db1ed61732537d076.diff

LOG: [InstCombine] Transform `(shift X,Or(Y,BitWidth-1))` -> `(shift X,BitWidth-1)`

shl : https://alive2.llvm.org/ce/z/_B7Qca
lshr: https://alive2.llvm.org/ce/z/6eXz_W
ashr: https://alive2.llvm.org/ce/z/oGEx-q

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D145326

Added: 
    

Modified: 
    llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
    llvm/test/Transforms/InstCombine/shift.ll

Removed: 
    


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diff  --git a/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp b/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
index 0f8a327177ec..6f69e123014c 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
@@ -483,6 +483,9 @@ Instruction *InstCombinerImpl::commonShiftTransforms(BinaryOperator &I) {
   if (Instruction *Logic = foldShiftOfShiftedBinOp(I, Builder))
     return Logic;
 
+  if (match(Op1, m_Or(m_Value(), m_SpecificInt(BitWidth - 1))))
+    return replaceOperand(I, 1, ConstantInt::get(Ty, BitWidth - 1));
+
   return nullptr;
 }
 

diff  --git a/llvm/test/Transforms/InstCombine/shift.ll b/llvm/test/Transforms/InstCombine/shift.ll
index 845bc079997a..91036b60c270 100644
--- a/llvm/test/Transforms/InstCombine/shift.ll
+++ b/llvm/test/Transforms/InstCombine/shift.ll
@@ -2071,8 +2071,7 @@ define i32 @shl2_cttz(i32 %x) {
 ; shift (X, amt | bitwidth - 1) -> shift (X, bitwidth - 1)
 define i6 @shl_or7_eq_shl7(i6 %x, i6 %c) {
 ; CHECK-LABEL: @shl_or7_eq_shl7(
-; CHECK-NEXT:    [[AMT:%.*]] = or i6 [[C:%.*]], 5
-; CHECK-NEXT:    [[Y:%.*]] = shl nsw i6 [[X:%.*]], [[AMT]]
+; CHECK-NEXT:    [[Y:%.*]] = shl nsw i6 [[X:%.*]], 5
 ; CHECK-NEXT:    ret i6 [[Y]]
 ;
   %amt = or i6 %c, 5
@@ -2083,8 +2082,7 @@ define i6 @shl_or7_eq_shl7(i6 %x, i6 %c) {
 
 define <2 x i8> @lshr_vec_or7_eq_shl7(<2 x i8> %x, <2 x i8> %c) {
 ; CHECK-LABEL: @lshr_vec_or7_eq_shl7(
-; CHECK-NEXT:    [[AMT:%.*]] = or <2 x i8> [[C:%.*]], <i8 7, i8 7>
-; CHECK-NEXT:    [[Y:%.*]] = lshr exact <2 x i8> [[X:%.*]], [[AMT]]
+; CHECK-NEXT:    [[Y:%.*]] = lshr exact <2 x i8> [[X:%.*]], <i8 7, i8 7>
 ; CHECK-NEXT:    ret <2 x i8> [[Y]]
 ;
   %amt = or <2 x i8> %c, <i8 7, i8 7>
@@ -2095,8 +2093,7 @@ define <2 x i8> @lshr_vec_or7_eq_shl7(<2 x i8> %x, <2 x i8> %c) {
 
 define <2 x i8> @ashr_vec_or7_eq_ashr7(<2 x i8> %x, <2 x i8> %c) {
 ; CHECK-LABEL: @ashr_vec_or7_eq_ashr7(
-; CHECK-NEXT:    [[AMT:%.*]] = or <2 x i8> [[C:%.*]], <i8 7, i8 7>
-; CHECK-NEXT:    [[Y:%.*]] = ashr <2 x i8> [[X:%.*]], [[AMT]]
+; CHECK-NEXT:    [[Y:%.*]] = ashr <2 x i8> [[X:%.*]], <i8 7, i8 7>
 ; CHECK-NEXT:    ret <2 x i8> [[Y]]
 ;
   %amt = or <2 x i8> %c, <i8 7, i8 7>