[llvm] 9bb409f - [InstCombine] Add tests for transform `(shift X, (Or Y, BitWidth-1))`; NFC

[Noah Goldstein via llvm-commits]

Author: Noah Goldstein
Date: 2023-03-06T20:29:57-06:00
New Revision: 9bb409ff1d0c21bca5981b9f3e0dbf668d320c3c

URL: https://github.com/llvm/llvm-project/commit/9bb409ff1d0c21bca5981b9f3e0dbf668d320c3c
DIFF: https://github.com/llvm/llvm-project/commit/9bb409ff1d0c21bca5981b9f3e0dbf668d320c3c.diff

LOG: [InstCombine] Add tests for transform `(shift X,(Or Y, BitWidth-1))`; NFC

Differential Revision: https://reviews.llvm.org/D145334

Added: 
    

Modified: 
    llvm/test/Transforms/InstCombine/shift.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/Transforms/InstCombine/shift.ll b/llvm/test/Transforms/InstCombine/shift.ll
index 652b2a095e8d..845bc079997a 100644
--- a/llvm/test/Transforms/InstCombine/shift.ll
+++ b/llvm/test/Transforms/InstCombine/shift.ll
@@ -2067,3 +2067,51 @@ define i32 @shl2_cttz(i32 %x) {
   %shl = shl i32 2, %tz
   ret i32 %shl
 }
+
+; shift (X, amt | bitwidth - 1) -> shift (X, bitwidth - 1)
+define i6 @shl_or7_eq_shl7(i6 %x, i6 %c) {
+; CHECK-LABEL: @shl_or7_eq_shl7(
+; CHECK-NEXT:    [[AMT:%.*]] = or i6 [[C:%.*]], 5
+; CHECK-NEXT:    [[Y:%.*]] = shl nsw i6 [[X:%.*]], [[AMT]]
+; CHECK-NEXT:    ret i6 [[Y]]
+;
+  %amt = or i6 %c, 5
+  ;; nsw not needed for transform, just check that we propagate.
+  %y = shl nsw i6 %x, %amt
+  ret i6 %y
+}
+
+define <2 x i8> @lshr_vec_or7_eq_shl7(<2 x i8> %x, <2 x i8> %c) {
+; CHECK-LABEL: @lshr_vec_or7_eq_shl7(
+; CHECK-NEXT:    [[AMT:%.*]] = or <2 x i8> [[C:%.*]], <i8 7, i8 7>
+; CHECK-NEXT:    [[Y:%.*]] = lshr exact <2 x i8> [[X:%.*]], [[AMT]]
+; CHECK-NEXT:    ret <2 x i8> [[Y]]
+;
+  %amt = or <2 x i8> %c, <i8 7, i8 7>
+  ;; exact not needed for transform, just check that we propagate.
+  %y = lshr exact <2 x i8> %x, %amt
+  ret <2 x i8> %y
+}
+
+define <2 x i8> @ashr_vec_or7_eq_ashr7(<2 x i8> %x, <2 x i8> %c) {
+; CHECK-LABEL: @ashr_vec_or7_eq_ashr7(
+; CHECK-NEXT:    [[AMT:%.*]] = or <2 x i8> [[C:%.*]], <i8 7, i8 7>
+; CHECK-NEXT:    [[Y:%.*]] = ashr <2 x i8> [[X:%.*]], [[AMT]]
+; CHECK-NEXT:    ret <2 x i8> [[Y]]
+;
+  %amt = or <2 x i8> %c, <i8 7, i8 7>
+  %y = ashr <2 x i8> %x, %amt
+  ret <2 x i8> %y
+}
+
+; Negative test not bitwidth - 1
+define <2 x i8> @ashr_vec_or6_fail(<2 x i8> %x, <2 x i8> %c) {
+; CHECK-LABEL: @ashr_vec_or6_fail(
+; CHECK-NEXT:    [[AMT:%.*]] = or <2 x i8> [[C:%.*]], <i8 6, i8 6>
+; CHECK-NEXT:    [[Y:%.*]] = ashr <2 x i8> [[X:%.*]], [[AMT]]
+; CHECK-NEXT:    ret <2 x i8> [[Y]]
+;
+  %amt = or <2 x i8> %c, <i8 6, i8 6>
+  %y = ashr <2 x i8> %x, %amt
+  ret <2 x i8> %y
+}