[PATCH] D145370: [AArch64] Fix N2 SchedModel for arithmetic ops with LSL ≤ 4

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

The add/sub sounds like a nice change.

>From what I can tell all the logical operators (and/orr/etc) that don't set flags are latency 1, throughput 4. The ones that set flags (ands/bics) should be lat:2 throughput:2.



================
Comment at: llvm/lib/Target/AArch64/AArch64SchedPredNeoverse.td:17
+// Check for LSL shift <= 4
+def NeoverseCheapLSL : MCSchedPredicate<
+                         CheckAll<
----------------
This is a quite common pattern and I think already exists somewhere. Can you move it somewhere shared?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D145370/new/

https://reviews.llvm.org/D145370