[PATCH] D142998: [SVE][codegen] Add few more tests for MUL followed by ADD/SUB (NFC)

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added a comment.

Fair enough. Sorry for the misunderstanding.



================
Comment at: llvm/test/CodeGen/AArch64/sve-generate-pseudo.ll:4
+define <vscale x 16 x i8> @mls_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) {
+; CHECK: {{.*}} MLS_ZPmZZ_B {{.*}}
+  %1 = mul <vscale x 16 x i8> %a, %b
----------------
Please use `update_llc_test_checks.py` to autogenerate the `CHECK` lines.  Or perhaps why not just place all the tests within sve-int-arith.ll? given they're related.


================
Comment at: llvm/test/CodeGen/AArch64/sve-generate-pseudo.ll:10
+
+define <vscale x 16 x i8> @mla_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) {
+; CHECK: {{.*}} MLA_ZPmZZ_B {{.*}}
----------------
Please include equivalent tests for the other supports element types (i.e. i16, i32 and i64).


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D142998/new/

https://reviews.llvm.org/D142998