[PATCH] D144388: [X86] Revise Alderlake P-Core schedule model

[Haohai, Wen via Phabricator via llvm-commits]

HaohaiWen added a comment.

Should we always use worst latency in schedule model like TTI?


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  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D144388/new/

https://reviews.llvm.org/D144388