[PATCH] D144388: [X86] Revise Alderlake P-Core schedule model

[Noah Goldstein via Phabricator via llvm-commits]

goldstein.w.n added a comment.

In D144388#4170437 <https://reviews.llvm.org/D144388#4170437>, @HaohaiWen wrote:

> According to optimization manual, back to back ADD latency is 2 cycles. What uops.info tested was not back to back ADD latency.
>
>> Back-to-back ADD/SUB operations that are both executed on the Fast Adder unit perform the operations
>> in two cycles.
>> •
>> In 128/256-bit, back-to-back ADD/SUB operations executed on the Fast Adder unit perform the
>> operations in two cycles.
>> •
>> In 512-bit, back-to-back ADD/SUB operations are executed in two cycles if both operations use the
>> Fast Adder unit on port 5.
>> The following instructions are executed by the Fast Adder unit:
>> •
>> (V)ADDSUBSS/SD/PS/PD
>> •
>> (V)ADDSS/SD/PS/PD
>> •
>> (V)SUBSS/SD/PS/PD

2c latency in just a special case isn't really 2c latency. That's like saying HSW has 4c L1D latency b.c of the weird pointer chasing case.

I only tested back-to-back so can't say, but if it's 3c in other cases (as measured by uops.info) maybe should change back?


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https://reviews.llvm.org/D144388