[PATCH] D145299: [X86] Generate better code for std::bit_ceil

Sun Mar 5 11:47:42 PST 2023

spatel added a comment.

In D145299#4169855 <https://reviews.llvm.org/D145299#4169855>, @nikic wrote:

> In D145299#4169706 <https://reviews.llvm.org/D145299#4169706>, @spatel wrote:
>
>> In D145299#4169702 <https://reviews.llvm.org/D145299#4169702>, @RKSimon wrote:
>>
>>> What is preventing is from performing this in InstCombine? I don't think this pattern will emerge in SelectionDAG
>>
>> I haven't found a way to avoid a poison shift in IR without doing a cmp+select or umax yet. I think we're relying on the x86-specific behavior of masking the shift amount to make that part of the logic disappear in this patch.
>
> Well, we could also do what is being proposed here and mask the shift amount: https://alive2.llvm.org/ce/z/FD_9Sh On x86, that happens to be free. I'm not sure this makes sense as an IR canonicalization though.

Oops - yes, I was overlooking that direct translation. It's shorter IR with the mask, and the backend should already account for the mask if it can be removed, so yes, that seems like a good improvement.

I think we still have several potential canonicalizations to deal with if we want a robust solution (see my earlier Alive2 link with variations with umax and shift-right).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D145299/new/

https://reviews.llvm.org/D145299