[PATCH] D145159: [AMDGPU] Match med3 for (max (min ..))

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

In D145159#4164559 <https://reviews.llvm.org/D145159#4164559>, @Pierre-vh wrote:

> In D145159#4164555 <https://reviews.llvm.org/D145159#4164555>, @foad wrote:
>
>> Is there a reason this is implemented in C++ instead of instruction selection patterns?
>
> It's a DAG combine, it isn't creating a V_MED3 directly but the AMDGPUsmed3 DAG op so it can be matched by other ISel pattern
> Can we write those in TableGen? I thought we couldn't

I think the constant value case would just be more annoying to handle in tablegen, but I think it's possible. If there's value in other patterns checking the med3, it makes sense to keep as a combine



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Comment at: llvm/test/CodeGen/AMDGPU/saddsat.ll:27
+; GFX8-NEXT:    v_mov_b32_e32 v1, 0x7f
+; GFX8-NEXT:    v_med3_i32 v0, v0, s4, v1
 ; GFX8-NEXT:    s_setpc_b64 s[30:31]
----------------
foad wrote:
> Pierre-vh wrote:
> > Another example, this time it's 2 more instructions so it's a bit worse even.
> The extra one is because you're using v_med3_i32 for a 16-bit operation. v_med3_i16 was introduced in gfx9.
This should have been filtered out by the hasMed3_16 check


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