[PATCH] D145159: [AMDGPU] Match med3 for (max (min ..))

[Pierre van Houtryve via Phabricator via llvm-commits]

Pierre-vh added a comment.

In D145159#4164555 <https://reviews.llvm.org/D145159#4164555>, @foad wrote:

> Is there a reason this is implemented in C++ instead of instruction selection patterns?

It's a DAG combine, it isn't creating a V_MED3 directly but the AMDGPUsmed3 DAG op so it can be matched by other ISel pattern
Can we write those in TableGen? I thought we couldn't


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https://reviews.llvm.org/D145159