[PATCH] D144388: [X86] Revise Alderlake P-Core schedule model

[Haohai, Wen via Phabricator via llvm-commits]

HaohaiWen added a comment.

In D144388#4163636 <https://reviews.llvm.org/D144388#4163636>, @ValZapod wrote:

> Should not such issues be first fixed in uops site? How can you be sure it is not just a typo in Intel docs, which has a lot of them?

AFAIK, vadd latency should be 2 cycles, not 3 in uops site. I guess data in intel doc was not measured in same way like uops site.
Do you know which data in Intel doc is wrong? We can provide feedback to fix it.


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https://reviews.llvm.org/D144388