[PATCH] D144388: [X86] Revise Alderlake P-Core schedule model

Wed Mar 1 21:45:56 PST 2023

ValZapod added a comment.

In D144388#4163661 <https://reviews.llvm.org/D144388#4163661>, @goldstein.w.n wrote:

> In D144388#4163636 <https://reviews.llvm.org/D144388#4163636>, @ValZapod wrote:
>
>> Should not such issues be first fixed in uops site? How can you be sure it is not just a typo in Intel docs, which has a lot of them?
>
> +1

The worst part uops (and https://uica.uops.info/ ) do not insert numbers manually, okay? They use automatic approaches, and this means (if true, not Intel typo) bugs in their instruments. Moreover energy utilised and number of transistors/analog devices used and flipped may be once again different, that is Intel PCH OS Minix root exploit level information though. See also genius article and next level: Minix OS hacks. https://blog.can.ac/2021/03/22/speculating-x86-64-isa-with-one-weird-trick/

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D144388/new/

https://reviews.llvm.org/D144388