[PATCH] D145155: [RISCV] Enable interleaved access vectorization

[Luke Lau via Phabricator via llvm-commits]

luke added inline comments.


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Comment at: llvm/test/Transforms/LoopVectorize/RISCV/interleaved-accesses-expensive.ll:4
+
+; This element type isn't a supported SEW so this shouldn't be interleaved
+define void @load_store_expensive(ptr %p) {
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We don't need to check if the type is legal in `getInterleavedMemoryOpCost`, since the loop vectorizer already checks if the type needs to be split by calling `TTI.getNumberOfParts`


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D145155/new/

https://reviews.llvm.org/D145155