[PATCH] D145155: [RISCV] Enable interleaved access vectorization

[Luke Lau via Phabricator via llvm-commits]

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The loop vectorizer supports generating interleaved loads and stores via
shuffle patterns for fixed length vectors.
This enables it for RISC-V, since interleaved shuffle patterns can be
lowered to vlseg/vsseg in https://reviews.llvm.org/D145022


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D145155

Files:
  llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
  llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
  llvm/test/Transforms/LoopVectorize/RISCV/interleaved-accesses-expensive.ll
  llvm/test/Transforms/LoopVectorize/RISCV/interleaved-accesses.ll
  llvm/test/Transforms/LoopVectorize/RISCV/zvl32b.ll

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