[PATCH] D145113: [DAGCombiner][AArch64] Constant fold ISD::VSCALE if VScaleMin==VScaleMax.

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added a comment.

Not a strongly held view but is there value in restricting the combine to pre-operation legalisation? I ask because I wonder if they'll be a point during legalisation where somebody specifically wants the `ISD::VSCALE` node.   Perhaps a different/better option is to move the logic into `SelectionDAG::getVScale()`, which can take a default false bool to disable the optimisation?


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