[PATCH] D145129: [X86] Fix undefined access in `matchUnaryPermuteShuffle`

[Noah Goldstein via Phabricator via llvm-commits]

goldstein.w.n updated this revision to Diff 501705.
goldstein.w.n added a comment.

Cover second case


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D145129/new/

https://reviews.llvm.org/D145129

Files:
  llvm/lib/Target/X86/X86ISelLowering.cpp


Index: llvm/lib/Target/X86/X86ISelLowering.cpp
===================================================================
--- llvm/lib/Target/X86/X86ISelLowering.cpp
+++ llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -14118,10 +14118,10 @@
     V = V2;
   }
 
-  if (BitwiseOnly && (Opcode == X86ISD::VSHLDQ || Opcode == X86ISD::VSRLDQ))
+  if (ShiftAmt < 0)
     return SDValue();
 
-  if (ShiftAmt < 0)
+  if (BitwiseOnly && (Opcode == X86ISD::VSHLDQ || Opcode == X86ISD::VSRLDQ))
     return SDValue();
 
   assert(DAG.getTargetLoweringInfo().isTypeLegal(ShiftVT) &&
@@ -38829,12 +38829,13 @@
       int ShiftAmt =
           matchShuffleAsShift(ShuffleVT, Shuffle, MaskScalarSizeInBits, Mask, 0,
                               Zeroable, Subtarget);
-      // Byte shifts can be slower so only match them on second attempt.
-      if (Order == 0 &&
-          (Shuffle == X86ISD::VSHLDQ || Shuffle == X86ISD::VSRLDQ))
-        continue;
       if (0 < ShiftAmt && (!ShuffleVT.is512BitVector() || Subtarget.hasBWI() ||
                            32 <= ShuffleVT.getScalarSizeInBits())) {
+        // Byte shifts can be slower so only match them on second attempt.
+        if (Order == 0 &&
+            (Shuffle == X86ISD::VSHLDQ || Shuffle == X86ISD::VSRLDQ))
+          continue;
+
         PermuteImm = (unsigned)ShiftAmt;
         return true;
       }


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