[PATCH] D145085: [RISCV] Lower interleaved accesses

[Luke Lau via Phabricator via llvm-commits]

luke added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:1805
   if (ScalarTy->isPointerTy())
-    return true;
+    return Subtarget.is64Bit() ? Subtarget.hasVInstructionsI64() : true;
 
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The idea here is that opaque pointer types will be lowered to i32 or i64 depending on the xlen, but the subtarget might only have `ve32x` when on `rv64`: Therefore `ptr` isn't a legal element type.
I originally intended to split this out into a separate change, but it doesn't actually affect any test cases since they seem to be covered by `isTypeLegal`, which is used in the gather/scatter lowering pass. 


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:14991-15008
+  // Check that the vlseg/vsseg pseudo exists for the type and NF
+  MVT VT =
+      getContainerForFixedLengthVector(getValueType(DL, VTy).getSimpleVT());
+  RISCVII::VLMUL LMUL = getLMUL(VT);
+  unsigned Log2SEW = Log2_32(VT.getScalarSizeInBits());
+  if (IsVsseg) {
+    const RISCV::VSSEGPseudo *P =
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The existence of the actual pseudo is checked here because we need to make sure we only lower when this condition from the spec is met:
> The EMUL setting must be such that EMUL * NFIELDS ≤ 8, otherwise the instruction encoding is reserved.

It's hairy having to extract the value type, but this seems to be what the gather/scatter does here too.

Also, because we reject illegal types with `!isTypeLegal(getValueType(DL, VTy))`, we don't support segmented loads/stores of `v3i32` etc. 
Ideally we could still use them here and have them widened to `v4i32` etc. later, but it's blocked on us needing the MVT to check for the existence of the pseudo.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D145085/new/

https://reviews.llvm.org/D145085