[PATCH] D145085: [RISCV] Lower interleaved accesses

Luke Lau via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Mar 1 10:33:07 PST 2023


luke created this revision.
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This enables the interleaved access pass on O1 <https://reviews.llvm.org/owners/package/1/> and above, and causes
interleaving/deinterleaving shuffles of fixed length vectors with
stores/loads to be lowered into vssegN/vlsegN.

We need to be careful and make sure that we only lower vsseg/vlseg
whenever we know the fixed vector type will fit within the minimum vlen,
and that the interleaving factor is supported for the given LMUL.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D145085

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
  llvm/test/CodeGen/RISCV/O3-pipeline.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access-zve32x.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access-zvl32b.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shufflevector-vnsrl.ll
  llvm/test/Transforms/InterleavedAccess/RISCV/interleaved-accesses.ll
  llvm/test/Transforms/InterleavedAccess/RISCV/zve32x.ll
  llvm/test/Transforms/InterleavedAccess/RISCV/zvl32b.ll

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