[PATCH] D145071: [clang][RISCV] Set HasLegalHalfType to true if zfh is enabled

[Alex Bradbury via Phabricator via llvm-commits]

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The desired semantics for HasLegalHalfType are slightly unclear in that the comment for HasLegalHalfType says "True if the backend supports operations on the half LLVM IR type." Which operations? We get very limited scalar operations with zfhmin, more with zfh, and vector support with zvfh. While the comment for hasLegalHalfType() says "Determine whether _Float16 is supported on this target."

The only target-independent use of hasLegalHalfType appears to be in the logic for UseExcessPrecision added in D136176 <https://reviews.llvm.org/D136176>.

Sharing this trivial path for review for a second opinion on what the "correct" answer is for RISC-V. If we agree this is correct, this patch should likely be updated with a test that tries to demonstrate a difference in -fexcess-precision logic.


https://reviews.llvm.org/D145071

Files:
  clang/lib/Basic/Targets/RISCV.cpp


Index: clang/lib/Basic/Targets/RISCV.cpp
===================================================================
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -315,6 +315,9 @@
   if (ABI.empty())
     ABI = ISAInfo->computeDefaultABI().str();
 
+  if (ISAInfo->hasExtension("zfh"))
+    HasLegalHalfType = true;
+
   return true;
 }
 


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