[PATCH] D144954: [AMDGPU][AsmParser][NFC] Simplify parsing cache policies.
Ivan Kosarev via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Mar 1 04:34:34 PST 2023
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGb06e5ad8a659: [AMDGPU][AsmParser][NFC] Simplify parsing cache policies. (authored by kosarev).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D144954/new/
https://reviews.llvm.org/D144954
Files:
llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
Index: llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -6027,28 +6027,21 @@
unsigned AMDGPUAsmParser::getCPolKind(StringRef Id, StringRef Mnemo,
bool &Disabling) const {
- Disabling = Id.startswith("no");
+ Disabling = Id.consume_front("no");
if (isGFX940() && !Mnemo.startswith("s_")) {
return StringSwitch<unsigned>(Id)
.Case("nt", AMDGPU::CPol::NT)
- .Case("nont", AMDGPU::CPol::NT)
.Case("sc0", AMDGPU::CPol::SC0)
- .Case("nosc0", AMDGPU::CPol::SC0)
.Case("sc1", AMDGPU::CPol::SC1)
- .Case("nosc1", AMDGPU::CPol::SC1)
.Default(0);
}
return StringSwitch<unsigned>(Id)
.Case("dlc", AMDGPU::CPol::DLC)
- .Case("nodlc", AMDGPU::CPol::DLC)
.Case("glc", AMDGPU::CPol::GLC)
- .Case("noglc", AMDGPU::CPol::GLC)
.Case("scc", AMDGPU::CPol::SCC)
- .Case("noscc", AMDGPU::CPol::SCC)
.Case("slc", AMDGPU::CPol::SLC)
- .Case("noslc", AMDGPU::CPol::SLC)
.Default(0);
}
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