[PATCH] D145004: [AArch64] More patterns to generate LD1R vector splats

[Dave Green via Phabricator via llvm-commits]

dmgreen accepted this revision.
dmgreen added a comment.
This revision is now accepted and ready to land.

Sounds good. I'm a little surprised that if we have a vector load where only one lane it demanded that we don't change it into a scalar load.

Can you add this as a multi-use test case. Otherwise LGTM:

  define <4 x i32> @shuffle2_multiuse(ptr %P) {
  ; CHECK-LABEL: shuffle2_multiuse:
  ; CHECK:       // %bb.0:
  ; CHECK-NEXT:    ldr q0, [x0]
  ; CHECK-NEXT:    dup v1.4s, v0.s[0]
  ; CHECK-NEXT:    dup v0.4s, v0.s[1]
  ; CHECK-NEXT:    add v0.4s, v1.4s, v0.4s
  ; CHECK-NEXT:    ret
    %lv2i32 = load <4 x i32>, ptr %P
    %B = shufflevector <4 x i32> %lv2i32, <4 x i32> undef, <4 x i32> zeroinitializer
    %C = shufflevector <4 x i32> %lv2i32, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
    %D = add <4 x i32> %B, %C
    ret <4 x i32> %D
  }


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