[PATCH] D145004: [AArch64] More patterns to generate LD1R vector splats

[Sjoerd Meijer via Phabricator via llvm-commits]

SjoerdMeijer created this revision.
SjoerdMeijer added reviewers: dmgreen, fhahn, david-arm, paulwalker-arm.
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We are missing patterns to generate vector splats using LD1R. 
A shuffle vector with all 0s is a vector splat:

  %lv2i32 = load <2 x i32>, ptr %P
  %B = shufflevector <2 x i32> %lv2i32, <2 x i32> undef, <2 x i32> zeroinitializer

for which we can generate a LD1R if the operands are a load and undef. This was inspired by the tests in:

  llvm-project/llvm/test/Analysis/CostModel/AArch64/shuffle-load.ll

for which we don't generate LD1Rs.


https://reviews.llvm.org/D145004

Files:
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/test/CodeGen/AArch64/neon-vector-splat.ll

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