[PATCH] D144925: [RISCV][NFC] Replace the pseudos for instructions that depend on lmul with variants that encode the SEW into the name

[Michael Maitland via Phabricator via llvm-commits]

michaelmaitland added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:2041-2061
   foreach m = MxList in {
     defvar mx = m.MX;
-    defvar WriteVGatherV_MX = !cast<SchedWrite>("WriteVGatherV_" # mx);
-    defvar ReadVGatherV_MX = !cast<SchedRead>("ReadVGatherV_" # mx);
 
     foreach sew = EEWList in {
       defvar octuple_lmul = m.octuple;
       // emul = lmul * eew / sew
       defvar octuple_emul = !srl(!mul(octuple_lmul, eew), log2<sew>.val);
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nitinjohnraj wrote:
> michaelmaitland wrote:
> > `WriteVGatherV_MX_E` and `ReadVGatherV_MX_E` dont depend on `sew` from `EEWList`. Can we pull out the loop over `sews` from `SchedSEWSet<mx>.val` to simplify?
> Thanks for the review! We can certainly do that, but does it really simplify the code? It's a nested loop in either case, so I'm not clear which version performs better/looks simpler.
You are right. Good as you have it :)


================
Comment at: llvm/lib/Target/RISCV/RISCVScheduleV.td:41
+    if !eq(mx, "UpperBound") then
+      def name # "_" # mx : SchedWrite;
+    else
----------------
nitinjohnraj wrote:
> michaelmaitland wrote:
> > Why don't we make this case SEW aware?
> If I remember correctly, that was causing some other files to complain and I put this in as 
I think this should be sew aware here and below and we need to fix the other files that start complaining.


Repository:
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  https://reviews.llvm.org/D144925/new/

https://reviews.llvm.org/D144925