[PATCH] D144925: [RISCV][NFC] Replace the pseudos for instructions that depend on lmul with variants that encode the SEW into the name

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:2472
     defvar ReadVGatherX_MX = !cast<SchedRead>("ReadVGatherX_" # mx);
+    defvar ReadVGatherI_MX = !cast<SchedRead>("ReadVGatherI_" # mx);
 
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nitinjohnraj wrote:
> michaelmaitland wrote:
> > Why did we change `ReadVGatherV` to `ReadVGatherI`?
> After discussion with @craig.topper, we did this because otherwise we'd need to maintain both SEW-aware and SEW-unaware versions of `ReadVGatherV`:
> 1. The SEW-aware version on line 2481 for the `_VV` binary, which is SEW-aware itself
> 2. The SEW-unaware version for the `_VI` binary, which is not SEW aware
> 
> This change helps us generate only the SEW-aware `ReadVGatherV` SchedReads. I'd be glad to talk about this more if you think we should approach this differently though.
We should move this part to a separate patch. vrgather.vi, vrgather.vx, vrgather.vv are all sort of different.

Let's consider a uarch that splits a LMUL>1 into multiple subvectors acrosss multiple uops:
vrgather.vi knows at decode time which subvector of the full source is needed for the destination subvectors
vrgather.vx doesn't know until the scalar instruction executes which subvector of the full source is needed. But only one subvector will be needed.
vrgather.vv every subvector of the destination can be dependent on multiple subvectors of the source.


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  https://reviews.llvm.org/D144925/new/

https://reviews.llvm.org/D144925