[PATCH] D144900: [X86] Add DwarfRegNums for segment registers

[Alex Brachet via Phabricator via llvm-commits]

abrachet updated this revision to Diff 500877.

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D144900/new/

https://reviews.llvm.org/D144900

Files:
  llvm/lib/Target/X86/X86RegisterInfo.td
  llvm/test/MC/X86/dwarf-segment-register.s


Index: llvm/test/MC/X86/dwarf-segment-register.s
===================================================================
--- /dev/null
+++ llvm/test/MC/X86/dwarf-segment-register.s
@@ -0,0 +1,37 @@
+// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o %t.64
+// RUN: llvm-objdump --dwarf=frames %t.64 | FileCheck %s --check-prefixes=64,CHECK
+// RUN: llvm-mc -filetype=obj -triple i386-pc-linux-gnu %s -o %t.32
+// RUN: llvm-objdump --dwarf=frames %t.32 | FileCheck %s --check-prefixes=32,CHECK
+
+.cfi_startproc
+.cfi_offset %cs, -40
+.cfi_offset %ds, -32
+.cfi_offset %ss, -24
+.cfi_offset %es, -16
+.cfi_offset %fs, -8
+.cfi_offset %gs, 0
+.cfi_endproc
+
+// 64: reg51
+// 32: reg41
+// CHECK-SAME: -40
+
+// 64: reg53
+// 32: reg43
+// CHECK-SAME: -32
+
+// 64: reg52
+// 32: reg42
+// CHECK-SAME: -24
+
+// 64: reg50
+// 32: reg40
+// CHECK-SAME: -16
+
+// 64: reg54
+// 32: reg44
+// CHECK-SAME: -8
+
+// 64: reg55
+// 32: reg45
+// CHECK-SAME: 0
Index: llvm/lib/Target/X86/X86RegisterInfo.td
===================================================================
--- llvm/lib/Target/X86/X86RegisterInfo.td
+++ llvm/lib/Target/X86/X86RegisterInfo.td
@@ -320,12 +320,12 @@
 
 
 // Segment registers
-def CS : X86Reg<"cs", 1>;
-def DS : X86Reg<"ds", 3>;
-def SS : X86Reg<"ss", 2>;
-def ES : X86Reg<"es", 0>;
-def FS : X86Reg<"fs", 4>;
-def GS : X86Reg<"gs", 5>;
+def CS : X86Reg<"cs", 1>, DwarfRegNum<[51, -2, 41]>;
+def DS : X86Reg<"ds", 3>, DwarfRegNum<[53, -2, 43]>;
+def SS : X86Reg<"ss", 2>, DwarfRegNum<[52, -2, 42]>;
+def ES : X86Reg<"es", 0>, DwarfRegNum<[50, -2, 40]>;
+def FS : X86Reg<"fs", 4>, DwarfRegNum<[54, -2, 44]>;
+def GS : X86Reg<"gs", 5>, DwarfRegNum<[55, -2, 45]>;
 
 def FS_BASE : X86Reg<"fs.base", 0>, DwarfRegNum<[58, -2, -2]>;
 def GS_BASE : X86Reg<"gs.base", 0>, DwarfRegNum<[59, -2, -2]>;


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