[llvm] 58de24e - [RISCV] Add a check for integer setcc to RISCVDAGToDAGISel::selectCondOp
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sat Feb 25 10:42:18 PST 2023
Author: Craig Topper
Date: 2023-02-25T10:39:57-08:00
New Revision: 58de24ebbb352a2345de3ebe280db98468ae96e3
URL: https://github.com/llvm/llvm-project/commit/58de24ebbb352a2345de3ebe280db98468ae96e3
DIFF: https://github.com/llvm/llvm-project/commit/58de24ebbb352a2345de3ebe280db98468ae96e3.diff
LOG: [RISCV] Add a check for integer setcc to RISCVDAGToDAGISel::selectCondOp
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 851652029e22..66845aac27dd 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -2450,6 +2450,9 @@ bool RISCVDAGToDAGISel::selectCondOp(SDValue N, bool Inverse, SDValue &Val) {
SDValue LHS = N->getOperand(0);
SDValue RHS = N->getOperand(1);
+ if (!LHS.getValueType().isInteger())
+ return false;
+
// If the RHS side is 0, we don't need any extra instructions, return the LHS.
if (isNullConstant(RHS)) {
Val = LHS;
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