[PATCH] D144614: [LegalizeTypes][RISCV] Add a special case to ExpandIntRes_UADDSUBO for (uaddo X, 1).

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

In D144614#4147953 <https://reviews.llvm.org/D144614#4147953>, @reames wrote:

> Both this and the related patch for ADD seem like they could be covered by a single set of DAG combine rules.  Specifically:
> a + 1 < a ==> a + 1 == 0
> a - 1 > a ==> a + 1 == 0

I think there's a mistake there. I think this is correct.
a - 1 > a  ==> a==0

> (With the comparisons in the notation above being setcc nodes.)
>
> Would doing the more general form and removing the expansion specific bits be worthwhile?

I'm not sure it helps with this patch, the wide setcc gets split before DAG combine would see it. But it could replace the change I did to ExpandIntRes_ADDSUB and the code I put in TargetLowering::expandUADDSUBO a long time back.


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https://reviews.llvm.org/D144614