[PATCH] D144614: [LegalizeTypes][RISCV] Add a special case to ExpandIntRes_UADDSUBO for (uaddo X, 1).

[Philip Reames via Phabricator via llvm-commits]

reames added a comment.

Both this and the related patch for ADD seem like they could be covered by a single set of DAG combine rules.  Specifically:
a + 1 < a ==> a + 1 == 0
a - 1 > a ==> a + 1 == 0

(With the comparisons in the notation above being setcc nodes.)

Would doing the more general form and removing the expansion specific bits be worthwhile?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D144614/new/

https://reviews.llvm.org/D144614