[PATCH] D144393: [X86] Add schedule module for Gracemont

[Haohai, Wen via Phabricator via llvm-commits]

HaohaiWen added inline comments.


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Comment at: llvm/lib/Target/X86/X86.td:1082
+  // Gracemont
+  list<SubtargetFeature> GRTTuning = [TuningMacroFusion,
+                                      TuningSlow3OpsLEA,
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RKSimon wrote:
> goldstein.w.n wrote:
> > Imo GMT is more sensible than GRT.
> +1 GMT is more commonly used for Gracemont already
As I know, GRT is the common abbreviation for Gracemont in Intel.
TRT is Tremont. not TNT in llvm.


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Comment at: llvm/lib/Target/X86/X86ScheduleGRT.td:73
+// until 4 cycles after the memory operand.
+def : ReadAdvance<ReadAfterLd, 4>;
+
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goldstein.w.n wrote:
> Is this correct? 
Max lat for ADD (R32 M32) is 5 in uops.info. The extra load latency is 4.


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Comment at: llvm/lib/Target/X86/X86ScheduleGRT.td:537
+def : WriteRes<WriteVecMoveToGpr, [GRTPort20]> {
+  let Latency = 4;
+}
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goldstein.w.n wrote:
> According to uops.info its 9c.
Instructions using this schedule write may be overwrite by InstRW.
This 4 cycles is the most common value for all instructions using this SchedWrite.


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https://reviews.llvm.org/D144393