[PATCH] D144092: [RISCV] Lower interleave and deinterleave intrinsics

[Luke Lau via Phabricator via llvm-commits]

luke added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:6708
+    // Build up the index vector for interleaving the concatenated vector
+    // ...   3   3   2   2   1   1   0   0
+    SDValue Idx = DAG.getNode(ISD::SRL, DL, IdxVT, StepVec,
----------------
reames wrote:
> I think the comments are backwards here.  I believe the value you're actually computing is:
> // 0,0,1,1,2,2,.. etc.
> 
> This could simply be a "which order do we write vector lanes in" confusion, but this ordered doesn't match the deinterleave comment above either.  
I've been staring at the spec too long, they use backwards notation. I agree, keeping it in LLVM order makes more sense


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D144092/new/

https://reviews.llvm.org/D144092